PRELIMINARY DATA SHEET
256MB Unbuffered DDR SDRAM DIMM
EBD26UB8ALFA
(32M words
×
64 bits, 2 Banks)
Description
The EBD26UB8ALFA is 32M words
×
64 bits, 2 banks
Double Data Rate (DDR) SDRAM unbuffered module,
mounted 16 pieces of 128M bits DDR SDRAM
(EDD1208ALTA) sealed in TSOP package. Read and
write operations are performed at the cross points of
the CLK and the /CLK. This high-speed data transfer
is realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. An outline of
the products is 184-pin socket type package (dual lead
out). Therefore, it makes high density mounting
possible without surface mount technology. It provides
common data inputs and outputs.
Decoupling
capacitors are mounted beside each TSOP on the
module board.
Features
•
184-pin socket type dual in line memory module
(DIMM)
Outline: 133.35mm (Length)
×
31.75mm (Height)
×
4.00mm (Thickness)
Lead pitch: 1.27mm
•
2.5V power supply (VDD/VDDQ)
•
SSTL-2 interface for all inputs and outputs
•
Clock frequency: 133MHz/100MHz (max.)
•
Data inputs and outputs are synchronized with DQS
•
4 banks can operate simultaneously and
independently (Component)
•
Burst read/write operation
•
Programmable burst length: 2, 4, 8
Burst read stop capability
•
Programmable burst sequence
Sequential
Interleave
•
Start addressing capability
Even and Odd
•
Programmable /CAS latency (CL): 2, 2.5
•
4096 refresh cycles: 15.6µs (4096/64ms)
•
2 variations of refresh
Auto refresh
Self refresh
Document No. E0215E10 (Ver. 1.0)
Date Published September 2001 (K)
Printed in Japan
URL: http://www.elpida.com
C
Elpida Memory, Inc. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
EBD26UB8ALFA
Pin Description
Pin name
A0 to A11
BA0, BA1
DQ0 to DQ63
/RAS
/CAS
/WE
/CS0, /CS1
CKE0, CKE1
CLK0 to CLK2
/CLK0 to /CLK2
DQS0 to DQS7
DM0 to DM7/DQS9 to DQS16
SCL
SDA
SA0 to SA2
VDD
VDDQ
VDDSPD
VREF
VSS
VDDID
NC
Function
Address input
Row address
Column address
A0 to A11
A0 to A9
Bank select address
Data input/output
Row address strobe command
Column address strobe command
Write enable
Chip select
Clock enable
Clock input
Differential clock input
Input and output data strobe
Input mask
Clock input for serial PD
Data input/output for serial PD
Serial address input
Power for internal circuit
Power for DQ circuit
Power for serial EEPROM
Input reference voltage
Ground
VDD indentication flag
No connection
Preliminary Data Sheet E0215E10 (Ver. 1.0)
4
EBD26UB8ALFA
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Number of row address
Number of column address
Number of DIMM banks
Module data width
Module data width continuation
Bit7
1
0
0
0
0
0
0
0
Bit6
0
0
0
0
0
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
Bit5 Bit4
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
Bit3
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
Bit2
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
1
0
0
Bit1 Bit0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
Hex value
80H
08H
07H
0CH
0AH
02H
40H
00H
04H
75H
75H
A0H
75H
75H
80H
00H
80H
08H
00H
01H
0EH
04H
0CH
01H
02H
20H
00H
75H
A0H
A0H
75H
75H
80H
00H
Comments
128 bytes
256 bytes
DDR SDRAM
12
10
2
64
0
SSTL2
7.5ns
7.5ns
10ns
0.75ns
0.75ns
0.8ns
None.
Norm
×
8
None.
1 CLK
2,4,8
4
2, 2.5
0
1
Differential
Clock
VDD ± 0.2V
7.5ns
10ns
10ns
0.75ns
0.75ns
0.8ns
Voltage interface level of this assembly 0
DDR SDRAM cycle time, CL = 2.5
-7A
-75
-1A
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
10
SDRAM access from clock (tAC)
-7A
-75
-1A
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
SDRAM module attributes
SDRAM device attributes: General
Minimum clock cycle time at CL = 2
-7A
-75
-1A
24
Maximum data access time (tAC) from
0
clock at CL = 2
-7A
-75
-1A
0
1
0
25 to 26
Preliminary Data Sheet E0215E10 (Ver. 1.0)
5
Test/Measurement
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