AS9C25512M2018L-250BI datasheet, PDF

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AS9C25512M2018L-250BI: DescriptionDual-Port SRAM, 512KX18, 6.5ns, CMOS, PBGA256, BGA-256; Categorystorage storage; File Size1MB，30 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

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AS9C25512M2018L-250BI Overview

Dual-Port SRAM, 512KX18, 6.5ns, CMOS, PBGA256, BGA-256

AS9C25512M2018L-250BI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ALSC [Alliance Semiconductor Corporation]
Parts packaging code	BGA
package instruction	LBGA,
Contacts	256
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	6.5 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	S-PBGA-B256
JESD-609 code	e0
length	17 mm
memory density	9437184 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Number of functions	1
Number of terminals	256
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX18
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	17 mm
Base Number Matches	1

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September 2004

Preliminary Information

AS9C25512M2018L

AS9C25256M2018L

2.5V 512/256K X 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface

Features

• True Dual-Port memory cells that allow simulta-

neous access of the same memory location

• Organisation: 524,288/262,144 × 18

[1]

• Fully Synchronous, independent operation on

both ports

• Selectable Pipeline or Flow-Through output

mode

• Fast clock speeds in Pipeline output mode: 250

MHz operation (9Gbps bandwidth)

• Fast clock to data access: 2.8ns for Pipeline out-

put mode

• Asynchronous output enable control

• Fast OE access times: 2.8ns

• Double Cycle Deselect (DCD) for Pipeline Out-

put Mode

• 19/18

[1]

-bit counter with Increment, Hold and

Repeat features on each port

Note:

1. AS9C25512M2018L/AS9C25256M2018L

•

Dual Chip enables on both ports for easy

depth expansion

Interrupt and Collision Detection Features

2.5 V power supply for the core

LVTTL compatible, selectable 3.3V or

2.5V power supply for I/Os, addresses,

clock and control signals on each port

Snooze modes for each port for standby

operation

15mA typical standby current in power

down mode

Available in 256-pin Ball Grid Array

(BGA), 144-pin Thin Quad Flatpack

(TQFP) and 208-pin fine pitch Ball Grid

Array (fpBGA)

Supports JTAG features compliant with

IEEE 1149.1

Selection guide

Feature

Minimum cycle time

Maximum Pipeline clock frequency

Maximum Pipeline clock access time

Maximum flow-through clock frequency

Maximum flow-through clock access time

Maximum operating current

Maximum snooze mode current

-250

250

2.8

150

6.5

TBD

-200

200

3.4

133

7.5

350

-166

166

3.6

100

300

-133

7.5

133

4.2

260

Units

MHz

9/24/04; v.1.2

Alliance Semiconductor

P. 1 of 30

AS9C25512M2018L

AS9C25256M2018L

General Description

The AS9C25512M2018L/AS9C25256M2018L is a high-speed CMOS 9/4.5-Mbit synchronous Dual-Port Static Random Access Memory

device, organized as 524,288/262,144 × 18 bits. It incorporates a selectable Flow-Through/Pipeline output feature for user flexibility. Clock-

to-data valid time is 2.8ns at 250 MHz for “Pipeline output” mode of operation.

Each port contains a 19/18 bit linear burst counter on the input address register that can loop through the whole address sequence. After

externally loading the counter with the initial address, it can be Incremented or Held for the next cycle. A new address can also be Loaded or

the “Previous Loaded” address can be re-accessed (Repeated) using counter controls (More description to follow). The Registers on control,

data, and address inputs provide minimal setup and hold times.

The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. A particular port can write

to a certain location while another port is reading from the same location, but the validity of read data is not guaranteed. However, the

reading port is informed about the possible collision through its collision alert signal. The result of writing to the same location by more than

one port at the same time is undefined.

The Asynchronous Output Enable input pin allows asynchronous disabling of output buffers at any given time. The Byte Enable inputs

allow individual byte read/write operations (refer Byte Control Truth Table). An automatic power down feature, controlled by CE0 and CE1,

permits the on-chip circuitry of each port to enter a very low standby power mode.

AS9C25512M2018L/AS9C25256M2018L can support an operating voltage of either 3.3V or 2.5V on either or both ports, which is

controlled by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V. This device is available in 256-pin Ball Grid

Array (BGA), 208-pin fine pitch Ball Grid Array (fpBGA) and 144-pin Thin Quad Flatpack (TQFP)

Address Counter

The AS9C25512M2018L/AS9C25256M2018L carries an internal 19/18 bit address counter for each port which can loop through the entire

memory array. The Address counter features are discussed below:

Load:

Any required external address can be loaded on to the counter. This feature is similar to normal address load in conventional

memories.

Increment:

The address counter has the capability to internally increment the address value, potentially covering the entire memory array.

Once the whole address space is completed, the counter will wrap around. The address counter is not initailized on Power-up, hence a known

location has to be loaded before Increment operation.

Hold:

The value of the counter register can be held for an unlimited number of clock cycles by de-asserting ADS, INC, and RPT inputs.

Repeat:

The previously loaded address (loaded using a valid Load operation) can be re-accessed by asserting RPT input. A separate 19/18

bit register called “Mirror register” is used to hold the last loaded address.This register is not initialized on Power-up, hence a known

location has to be loaded before Repeat operation (Refer Counter control truth table for details).

9/24/04, v.1.2

Alliance Semiconductor

P. 3 of 30

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