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EDS2516APTA-60-E

Description
256M bits SDRAM
Categorystorage    storage   
File Size616KB,53 Pages
ManufacturerELPIDA
Websitehttp://www.elpida.com/en
Environmental Compliance
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EDS2516APTA-60-E Overview

256M bits SDRAM

EDS2516APTA-60-E Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerELPIDA
Parts packaging codeTSOP2
package instructionTSOP2, TSOP54,.46,32
Contacts54
Reach Compliance Codeunknow
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time5 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)166 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G54
JESD-609 codee6
length22.22 mm
memory density268435456 bi
Memory IC TypeSYNCHRONOUS DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals54
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP54,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1.2 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.002 A
Maximum slew rate0.25 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Bismuth (Sn/Bi)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
DATA SHEET
256M bits SDRAM
EDS2516APTA (16M words
×
16 bits)
Description
The EDS2516AP is a 256M bits SDRAM organized as
4,194,304 words
×
16 bits
×
4 banks. All inputs and
outputs are referred to the rising edge of the clock
input. It is packaged in standard 54-pin plastic TSOP
(II)
Pin Configurations
/xxx indicates active low signal.
54-pin plastic TSOP (II)
VDD
DQ0
VDDQ
Features
DQ1
DQ2
VSSQ
3.3V power supply
Clock frequency: 166MHz/133MHz (max.)
LVTTL interface
Single pulsed /RAS
×16
organization
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8, full page
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by UDQM and LDQM
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
2 types of TSOP (II) package
Sn-Pb solder
Lead free solder (Sn-Bi)
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
EO
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Document No. E0359E20 (Ver. 2.0)
Date Published January 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida
Memory, Inc. 2003-2005
L
od
Pr
A0 to A12,
BA0, BA1
(Top view)
UDQM,LDQM
Input/output mask
Address input
Bank select address
DQ0 to DQ15
Data-input/output
Chip select
/CS
Row address strobe
/RAS
Column address strobe
/CAS
Write enable
/WE
CKE
CLK
VDD
VSS
VDDQ
VSSQ
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
NC
Power for DQ circuit
Ground for DQ circuit
No connection
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