SI5348B-B06557-GMR datasheet, PDF

Datasheet> All Categories > semiconductor> Analog mixed-signal IC> SI5348B-B06557-GMR

SI5348B-B06557-GMR: DescriptionClock Synthesizer / Jitter Cleaner Network Synchronizer & Jitter Attenuator; Categorysemiconductor Analog mixed-signal IC; File Size846KB，54 Pages; ManufacturerSilicon Laboratories

Download Datasheet Parametric View All

SI5348B-B06557-GMR Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	SI5348B-B06557-GMR	-	-	View	Buy Now

SI5348B-B06557-GMR Overview

Clock Synthesizer / Jitter Cleaner Network Synchronizer & Jitter Attenuator

SI5348B-B06557-GMR Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Silicon Laboratories
Product Category	Clock Synthesizer / Jitter Cleaner
Packaging	Box

Preview

Download Datasheet

View All

Si5348 Rev D Data Sheet

Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary

(T-BC) and Slave (T-SC) Clocks

The Si5348 combines the industry’s smallest footprint and lowest power network syn-

chronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The

Si5348 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless

communications systems, and data center switches requiring both traditional and packet

based network synchronization.

The three independent DSPLLs

™

are individually configurable as a SyncE PLL, IEEE

1588 DCO or a general-purpose PLL for processor/FPGA clocking. The Si5348 can also

be used in legacy SETS systems needing Stratum 3/3E compliance. The optional digital-

ly controlled oscillator (DCO) mode provides precise timing adjustment to 1 ppt for 1588

(PTP) clock steering applications. The unique design of the Si5348 allows the TCXO/

OCXO reference input to determine the device’s frequency accuracy and stability. The

Si5348 is programmable via a serial interface with in-circuit programmable non-volatile

memory so it always powers up into a known configuration. Programming the Si5348 is

easy with

ClockBuilder Pro

™

software. Factory pre-programmed devices are also availa-

ble.

KEY FEATURES

• Three independent DSPLLs in a single

monolithic IC supporting flexible SyncE/

IEEE 1588 and SETS architectures

• Ultra-low jitter of 100 fs

• Input frequency range:

• External crystal: 48 to 54 MHz

• REF clock: 5 to 250 MHz

• Diff clock: 8 kHz to 750 MHz

• LVCMOS clock: 8 kHz to 250 MHz

• Output frequency range:

• Differential: 1 PPS to 712.5 MHz

• LVCMOS: 1 PPS to 250 MHz

• Meets the requirements of:

• ITU-T G.8273.2 T-BC

• ITU-T G.8262 (SyncE) EEC Options 1 &

• ITU-T G.812 Type III, IV

• ITU-T G.813 Option 1

• Telcordia GR-1244, GR-253

(Stratum-3/3E)

Applications:

• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2

• Telecom Boundary Clock (T-BC) as defined by ITU-T G.8273.2

• IEEE 1588 (PTP) slave clock synchronization

• Stratum 3/3E, G.812, G.813 network synchronization

48-54 MHz XTAL

OSC

IN3

IN4

IN0

IN1

IN2

÷FRAC

DSPLL A

Status Flags

I2C / SPI

Status Monitor

Control

NVM

DSPLL C

DSPLL D

TCXO/OCXO

REFb

REF

÷INT

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

Si5348

silabs.com

| Smart. Connected. Energy-friendly.

Rev. 1.0

Si5348 Rev D Data Sheet

Functional Description

3. Functional Description

The Si5348 offers three DSPLLs that have identical performance and flexibility which can be independently configured and controlled

through the serial interface. Each of the DSPLLs support locked, free-run, and holdover modes of operation with an optional DCO mode

for IEEE 1588 applications. The device requires an external crystal and an external reference (TCXO or OCXO) to operate. The refer-

ence input (REF/REFb) determines the frequency accuracy and stability while in free-run and holdover modes. The external crystal

completes the internal oscillator circuit (OSC) which is used by the DSPLL for intrinsic jitter performance. There are three main inputs

(IN0 - IN2) for synchronizing the DSPLLs. Input selection can be manual or automatically controlled using an internal state machine.

Two additional manually selected inputs are available to DSPLL D. Any of the output clocks (OUT0 to OUT6) can be configured to any

of the DSPLLs using a flexible crosspoint connection. Output 6 is the only output that can be configured for a 1 Hz output to support 1

PPS.

3.1 Standards Compliance

Each of the DSPLLs meet the requirements of ITU-T G.8262 (SyncE), G.812, G.813, G.8273.2 (T-BC), in addition to Telcordia

GR-1244 and GR-253 as shown in the compliance report. The DCO feature enables IEEE1588 (PTP) implementations in addition to

hybrid SyncE + IEEE1588 (T-BC).

3.2 Frequency Configuration

The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile

memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), and integer output division

(Rn) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a

specific frequency plan are easily determined using the ClockBuilder Pro utility.

3.3 DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of input clock jitter and wander attenuation. Register configurable DSPLL loop

bandwidth settings of 1 mHz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally,

each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.

Table 3.1. Loop Bandwidth Requirements for North America

SONET (Telcordia)

GR-253 Stratum 3E

GR-253 Stratum 3

—

3.3.1 Fastlock Feature

Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting

a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-

ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. Once lock

acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting. The fastlock

feature can be enabled or disabled independently for each of the DSPLLs.

3.4 Modes of Operation

Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition

Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in

Figure 3.1 Modes of Operation

on page 4.

The following sections describe each of these modes in greater detail.

SDH (ITU-T)

G.812 Type III

G.812 Type IV

G.813 Option 1

SyncE (ITU-T)

—

G.8262 EEC Option 2

G.8262 EEC Option 1

Loop Bandwidth

0.001 Hz

<0.1 Hz

1 - 10 Hz

silabs.com

| Smart. Connected. Energy-friendly.

Rev. 1.0 | 3

Recommended Resources

Light chain circuit that glows along the four sides and from the inside out

One SIPU STR soft starter controls two motors

Clever use of LB1405 as audio signal amplifier circuit diagram

CXA1019S radio circuit

500 candela flash order circuit

Start-up delay intermittent operation circuit

【NXP Rapid IoT Review】W4 Bluetooth Review: [i=s]This post was last edited by johnrey on 2019-1-21 16:07[/i] [size=14px]Although the last round of sensor evaluation was not very smooth, and there are still many problems left unresolved, we fina...; johnrey RF/Wirelessly

Transistor problem: A signal of about 8M passes through C11 and the transistor. The 8M signal is generated by a capacitor three-point oscillation circuit, passes through C11, and then is amplified by the transistor. How ...; S3S4S5S6 Analog electronics

【AT-START-F425 Review】Using the USB flash drive file storage function to achieve data recording: Previously, we introduced how to use the USB flash drive file reading function to realize the digital photo frame function. This time, we will talk about using the file storage function to act as a da...; jinglixixi Domestic Chip Exchange

Creative Gift Winners List｜2020-2021 ON Semiconductor and Avnet IoT Creative Design Competition: [Competition Details] 2020-2021 ON Semiconductor and Avnet IoT Creative Design Competition[Award Collection Date] From now until January 20, 2021[How to claim the prize]Step1. Scan the QR code below o...; EEWORLD社区 onsemi and Avnet IoT Innovation Design Competition

E103-W01-BF test version use: I applied for the E103-W01-BF beta version. After passing the test, I will experience it according to the evaluation plan. The following is the evaluation plan: 1. Unboxing2. Observing the hardware de...; WJC1Person RF/Wirelessly

Pingtouge Xuantie CPU debugging system: For developers, a smooth debugging system and efficient debugging methods will effectively reduce information errors during the development process and improve development efficiency. This article wil...; 火辣西米秀 Domestic Chip Exchange

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components