9DB102BFLFT datasheet, PDF - EEWORLD Datasheet

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9DB102BFLFT: DescriptionClock Buffer 2 OUTPUT PCIE GEN2 BUFFER; Categorylogic logic; File Size156KB，13 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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9DB102BFLFT Overview

Clock Buffer 2 OUTPUT PCIE GEN2 BUFFER

9DB102BFLFT Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QSOP
package instruction	SSOP, SSOP20,.25
Contacts	20
Manufacturer packaging code	PCG20
Reach Compliance Code	compliant
ECCN code	EAR99
series	9DB
Input adjustment	DIFFERENTIAL
JESD-30 code	R-PDSO-G20
JESD-609 code	e3
length	8.65 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	20
Actual output times	2
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP20,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	0.185 ns
propagation delay (tpd)	0.15 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.025 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm
Base Number Matches	1

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DATASHEET

Two Output Differential Buffer for PCIe Gen1 & Gen2

Description

The

ICS9DB102

zero-delay buffer supports PCI Express

clocking requirements. The

ICS9DB102

is driven by a differential

SRC output pair from an ICS CK410/CK505-compliant main

clock. It attenuates jitter on the input clock and has a selectable

PLL Band Width to maximize performance in systems with or

without Spread-Spectrum clocking.

ICS9DB102

Features/Benefits

•

CLKREQ# pin for outputs 1 and 4/output enable for Express

Card applications

PLL or bypass mode/PLL can dejitter incoming clock

Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL’s

Spread Spectrum Compatible/tracks spreading input clock

for low EMI

SMBus Interface/unused outputs can be disabled

Industrial temperature range available

Output Features

•

2 - 0.7V current mode differential output pairs (HCSL)

Key Specifications

•

Cycle-to-cycle jitter < 35ps

Output-to-output skew < 25ps

Functional Block Diagram

CLKREQ0#

CLKREQ1#

PCIEX0

CLK_INT

SPREAD

COMPATIBLE

PLL

PCIEX1

C LK_IN C

PLL_BW

SMBDAT

SMBCLK

CONTROL

LOGIC

IREF

IDT

Two Output Differential Buffer for PCIe Gen1 & Gen2

852

REV Q 08/27/13

9DB102BFLFT Related Products

	9DB102BFLFT	9DB102BGILF
Description	Clock Buffer 2 OUTPUT PCIE GEN2 BUFFER	Clock Buffer 2 OUTPUT PCIE GEN2 BUFFER
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QSOP	TSSOP
package instruction	SSOP, SSOP20,.25	TSSOP-20
Contacts	20	20
Manufacturer packaging code	PCG20	PGG20
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
series	9DB	9DB
Input adjustment	DIFFERENTIAL	DIFFERENTIAL
JESD-30 code	R-PDSO-G20	R-PDSO-G20
JESD-609 code	e3	e3
length	8.65 mm	6.5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1	1
Number of functions	1	1
Number of terminals	20	20
Actual output times	2	2
Maximum operating temperature	70 °C	85 °C
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	TSSOP
Encapsulate equivalent code	SSOP20,.25	TSSOP20,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	0.185 ns	0.15 ns
propagation delay (tpd)	0.15 ns	0.15 ns
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.025 ns	0.025 ns
Maximum seat height	1.75 mm	1.2 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	COMMERCIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING
Terminal pitch	0.635 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	3.9 mm	4.4 mm
Base Number Matches	1	1

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