Delay and stretch circuit

Shown is a delay and morning width circuit consisting of inverters Gl,02 ( CD4069 ) and an RC integrating circuit . When the "NOT" gate OI outputs a high level , the C capacitor is charged through Rl and D, and the voltage on C quickly charges to the threshold level of the G2 input end. When Gl outputs low level , C discharges low level to the output terminal of Gl through R2 . Since R2-10Rl, the discharge time of C is 10 times of the charging time. Therefore, the G2 output pulse is delayed and broadened at the same time.