Monostable delay circuit composed of a single operational amplifier

The monostable delay circuit consists of a single operational amplifier connected to a voltage comparator. The circuit is as shown in the attached figure. It has the characteristics of simple circuit and convenient delay adjustment. 　　In normal state, the IC output remains low, and this state is stable. When the negative pulse is input to the inverting terminal through C1, the potential of the inverting terminal is lower than the potential of the non-inverting terminal, and the output terminal flips from low level to high level. This state is unstable. This high level is divided by R1 and R2 and then added to the non-inverting terminal of the IC, so that the potential of the non-inverting terminal is higher than the inverting terminal, thus maintaining the high level output. At the same time, the high level is charged by R3 and C2. When the voltage on C2 is charged to the point where the potential of the inverting terminal is higher than the potential of the non-inverting terminal, the output terminal flips to low level again. At this time, the potential of the non-inverting terminal is approximately zero, and the voltage on C2 is rapidly discharged to the output terminal through VD1, causing the circuit to accelerate back to the initial state. After the circuit is stable, the potential of the inverting terminal is still higher than the potential of the non-inverting terminal, so that the output low level is maintained. The delay time T of this circuit not only depends on R3 and C2, but also depends on the voltage dividing ratio of R1 and R2. Therefore, it is very convenient to adjust the delay time. You can adjust C2 and R3 for coarse delay adjustment, and adjust R2 for fine adjustment (if the voltage dividing ratio is 1/2 to 2/3, the delay accuracy is higher). However, the state of the circuit when powered on is random. To make the circuit have a unique output state after powering on, there are two methods: one is to add R4 to the circuit. In this way, when powering on, since the voltage on C1 cannot change suddenly, the power supply voltage is added to the inverting terminal through R4 and C1, which can set the output to a low level; second, connect a diode VD2 and a diode between the non-inverting terminal and the ground. Only switch S (shown as dashed line). If the output is high level when powering on, although this state is unstable, as mentioned above, it will take time T for the output to be low level, and in practice, the circuit often needs to be reset immediately when powering on. For this reason, S can be turned on first when powering on. If the output is high level, C2 can be charged to 0.7V to reset the circuit, which greatly shortens the power-on reset time of the circuit. After resetting, disconnect S and the circuit can work normally. In practical applications, if R1 is 100kΩ and R2 is 200kΩ, the voltage dividing ratio is 2/3 and the trigger delay time is approximately 0.7R3×C2. C1 can be taken as 0.1μF, and R3 can be taken as more than 10kΩ. The IC can use a single power supply op amp or comparator, such as LM324 or LM339.