Frequency divider composed of TTL decade counter

As shown in the figure, the frequency division circuit composed of TTL decade counters. In many cases, it is necessary to divide the pulse sequence by N (N is an integer). For example, the digital clock needs to be divided by 60 to obtain a pulse output with a repetition frequency of 1Hz; for another example, the time generator needs to divide the output frequency of the crystal oscillator. If the frequency division coefficient N≤10, it can be achieved with only one TTL binary-decimal counter SN7490. The frequency division in the usual TTL circuit uses a binary counter to output one pulse for every N input pulses. When the Nth pulse is input, the counter is reset and the most significant bit of the counter is used as the output. Therefore, the output of the counter can only have one state change for every N input pulses (i.e., high level changes to low level or low level changes to high level). If the output is required to be a pulse, a monostable multivibrator must be added.

The frequency divider made of a decimal counter SN7490 can have a frequency division factor of any integer between 2 and 10, which is mainly determined by which output terminal the reset input terminal (pins 2 and 3) is connected to. The connection method shown in the figure is 7-frequency division.