What is the impact between power supply noise and high-speed DAC phase noise?

Designers may be overwhelmed by all the noise sources that will be discussed in this article. A simple approach is to adopt some kind of "recommended solution"; but this is suboptimal for any specific design requirements. Of all device characteristics, noise can be a particularly challenging design topic to master. These challenges often lead to hearsay design rules and trial and error during development. This article will address the issue of phase noise, with the goal of using quantitative analysis to illustrate how to design around phase noise contributions in high-speed digital-to-analog converters. This article aims to obtain a "right first time" design method, that is, the design is no more and no less, just to meet the phase noise requirements.

Start with a clean slate and think of the DAC as a module. Noise can come from internal sources, as any real component will produce some kind of noise, or it can come from external noise sources. External noise sources can enter the DAC through any external connections, including power supplies, clocks, and digital interfaces. Figure 1 shows these possibilities. Each possible noise suspect will be studied individually below to understand its importance.

Figure 1. DAC phase noise sources

Discussing the digital interface first, it happens to be the easiest to deal with. Digital I/O is responsible for receiving digital sampled signals for output in the analog domain. It is well known that digital circuits and received waveforms are noisy, as shown in eye diagrams. From this point of view, the relevant question is: Can all this noise and activity penetrate different areas inside the DAC and manifest as phase noise? Of course, the digital interface may cause noise elsewhere, but the concern here is phase noise.

To demonstrate whether I/O is a concern, we compared the phase noise of the AD9162 family of high-speed DAC devices with and without the digital interface. Without a digital interface, the device's NCO mode generates waveforms internally, and the DAC effectively becomes a DDS generator. Figure 2 shows the experimental results.

Figure 2. Phase noise at different interpolations

The peak value of phase noise will vary depending on the specific conditions of the interface. Now what we are interested in is that the noise and all the curves are on top of each other. Therefore, for this product line, the interface is not an issue, although there may be spurious considerations due to system requirements. Having discovered that the interface is nothing to worry about, the next area of ​​interest is the clock.