Timing circuit composed of HD1438

 (1) Introduction to circuit principle. Before starting, the output of Q (@ pin) is low level , and the voltage on the external capacitor at T2 (② pin) terminal is U. ,,. When A
(④ foot) is o. When CD (③ pin) is 1, if B (⑤ pin) is triggered from the negative edge of 1-o, the output will latch the heron bit and Q will output high level. At the same
time, the external capacitor of T2 is discharged to the reference voltage Urd, and then charged through the external resistor. When the charge is equal to the reference voltage [,. &, the output latch is reset
. Q outputs low level and the circuit returns to the initial state.
    When the trigger is working, if the trigger is added before the Q output is low level, it is a pre-trigger. From the last trigger to the timing operation, the Q output is low level
. If CD enters 0. Then the external capacitor of T2 is charged to Umr/, the output latch is reset, and the circuit returns to the initial state. When CD is in 0 state
. If another pulse is input, the circuit will not operate
and the output will be low level.
    Q (⑥ pin) outputs high level ,
VT1 is turned on, causing relay K to operate, and
its contacts control the operation of related circuits. In the circuit
. Ri, Ci and Cz form a filter
circuit to prevent noise interference from causing the circuit to malfunction
. There is no need to connect the input pin to ground, that is, the ⑩, @
and @ pins are grounded.
    (2) Component parameter selection.
The selection of components is shown in Figure 3-25. There are no special
requirements.
    (3) The timing circuit composed of HD 14538 is shown in Figure 3-25.