Detailed explanation of the frame synchronization features in the AFE8092 AGC function

TI Transceiver chip is a highly integrated, high-performance radio frequency transceiver chip. The product architecture within the product family is rich in variety. In terms of product architecture, it includes zero-IF architecture transceivers represented by the AFE 77xx series, and RF direct acquisition architecture transceivers represented by the AFE80xx, AFE79xx, and AFE76xx series. In terms of product channel number, the minimum number of channels supported is 2T2R1F, 4T4R2F to 8T8R2F. At the same time, it also supports most radio frequency control functions, such as AC correction, PAP protection and AGC control functions. This article will briefly introduce the frame synchronization characteristics involved in the AGC function of AFE8092, and guide users to design parameter indicators based on radio frequency system requirements.

AFE8092 is TI's transceiver based on RF direct acquisition architecture. Due to its large bandwidth, high-performance RF indicators, and high flexibility, it is widely used in base station RF boards. Its block diagram is shown below. Among them, each transmit link contains a DAC with a sampling rate of up to 12Gsps , a bandwidth of up to 800MHz, and a DSA with a 40dB dynamic range of 0.125dB gain step (0.125dB provided by the digital part) for link gain adjustment. Its digital part includes DDC/DUC on the signal link, which can flexibly adapt to users' multi-band application scenarios, and also includes digital PAP functions to facilitate users in system robustness design.

Each receiving link includes an ADC with a maximum sampling rate of 4G sps , supports a maximum bandwidth of 400Mhz, and a 31dB step DSA for link gain control. Its digital part is similar to the transmit link, and also integrates AGC (Automatic Gain Control ) control function.

Figure 1 AFE8092 internal module architecture block diagram

In the application of base station radio frequency systems, due to the randomness of UE user access, the radio frequency signal power received by the receiver has time-varying characteristics. Based on the dynamic sensitivity of the radio frequency receiver, the receiver needs to be based on the signal power received by the base station. The gain of the signal link is updated in real time, so the AFE8092 integrates the AGC control function to realize the closed-loop gain control function in the system. The AGC control block diagram of the AFE8092 is shown below. The AGC control logic of the AFE8092 performs dynamic DSA gear adjustment based on the readback results of the RF power detector on the device's RX link.

Figure 2 AFE8092 receiving link AGC module schematic diagram

It can be seen that in the traditional AGC adjustment behavior mode, the information received by the AGC controller is only the radio frequency power detector information, and it is only responsible for the external signal power and is not responsible for the radio frequency wireless frame. But in TDD application scenarios, there is the concept of wireless frames. As shown in the figure below, TX is turned on in the D time slot, RX is turned on in the U time slot, and TX/RX is turned on in the S time slot according to a specific ratio. It can be seen that when switching from D to S, there is a situation where RX goes from off to on, and when switching from U to D, there is a situation where RX goes from on to off. This control mode has two problems in some scenarios: (1) In the middle of a single uplink time slot, the user does not want to trigger AGC;

(2) There may be a large signal at the beginning of the U time slot that the user wants to ignore and does not want to be included in the AGC event. Therefore, TI has integrated what we call the frame synchronization function in the AFE8092 based on this requirement.

Figure 3 Schematic diagram of wireless frame time slot

The core of the frame synchronization function is to freeze the DSA within a single uplink time slot, and then adjust the DSA when the RX open action (RX_EN) occurs next time. At the same time, the counter and the action of adjusting DSA need to be linked with RX_EN in terms of delay. There are two configuration modes linked to the system: AGC power statistics window length within a single RX time slot and AGC power statistics window length across RX time slots.

Figure 3 shows a schematic diagram of the behavior pattern of the AGC power statistics window length (the red box in the figure is the power statistics window) within a single RX time slot. The time flow direction is from left to right. A complete AGC adjustment cycle is as shown in the figure. Follow the steps marked in sequence. Let’s explain them one by one:

When the RX_EN signal comes, the RX channel is opened

After the RX_EN signal arrives, the AGC's power statistics counter and DSA do not take any action for a period of time (windowOffsetPeriod, user-configurable parameters).

After experiencing windowOffsetPeriod, there will be two actions:

If the AGC in the previous cycle triggered a control action, the DSA is adjusted to the expected value according to the AGC control logic.

AGC trigger threshold action: the power statistics counter is cleared and counted again

After a period of time (windowPeriod, user-configurable parameters), the counter is frozen and the DSA does not take any action.

Enter the next frame synchronization cycle

Figure 4 AGC power statistical window length

Figure 4 shows a schematic diagram of the behavior pattern of the AGC power statistics window length (the red box in the figure is the power statistics window) across a single RX time slot. It is somewhat similar to the example in Figure 4. The main difference is that in the example of Figure 5, after RX_EN is pulled low again, the RX counter will not be reset until the end of WindowPeriod. When WindowPeriod spans multiple RX_ENs, AGC will count the power of multiple uplink time slots and make DSA action decisions.

Figure 5 AGC power statistical window length