TMS320C6678 power-on configuration

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TMS320C6678 power-on configuration [Copy link]

1. What is the DSP power-on reset configuration? The DSP big-endian, little-endian, self-starting (boot) mode, PCIe mode, and network coprocessor clock selection need to be selected at power-on reset. How to select? Rely on locking the logic level of the DSP Device Configuration pins at power-on. How to set the logic level of the configuration pins? Generally, there are two ways: The first is to connect all the DSP configuration pins to the FPGA IO, and the FPGA is powered on to control (the FPGA reset DSP program is attached at the end of the article) The second is through external pull-up/pull-down resistors. Tip: A reasonable onboard design should ensure that all device input pins are at a valid level and cannot be left floating. This can be achieved through pull-up/pull-down resistors, of course, internal pull-up or external pull-up. The device generally implements pull-up/pull-down internally by evaluating the needs. However, some pins require external pull-up/pull-down. (1) Device configuration pins: These pins need to be output (C6678 configuration pins and GPIO are common pins) and undriven (high impedance). Even if the internal pull-up/pull-down resistors may meet the required level, external pull-up/pull-down is still required to ensure that the configuration is valid and to facilitate mode switching. (2) Other input pins: If the internal pull-up/pull-down does not meet the required level, an external pull-up/pull-down is required. 2. TMS320C6678 device configuration pins (1) LENDIAN: Determines the big and small endianness of the DSP. (2) BOOTMODE[12:0]: Determines the self-boot mode of the DSP (see BootLoader for the C66x DSP User Guide for details). (3) PCIESSMODE: Determines whether the PCIe subsystem is in EP, legacy EP or RC. (4) PCIESSEN: Determines whether the PICe subsystem is enabled. The default is not enabled. (5) PACKSEL: Determines whether the input clock of the network coprocessor is the core clock or the PASSCLK clock. 3. DSP power-on timing The DSP power-on timing is the power-on reset timing. Device initialization is divided into two stages: (1) All power supplies are stable, and different power supplies have power supply timings. (2) RESET, POR, and RESERFULL are pulled high in sequence, and of course the clock input is stable.