| EDA technology mainly refers to computer technology for ASIC design. Compared with traditional ASIC design technology, its characteristics are:
① The entire design process, including circuit system description, hardware design, simulation test, synthesis, debugging, software design, and even hardware system, is completed by computer; ②
The design technology is directly oriented to users, that is, the passive user of ASICs may also be the active designer of ASICs;
③ There are more ways to realize ASICs, that is, in addition to traditional ASIC devices, it can also be realized through programmable devices such as FPGA, CPLD, ispPAC, FPSC, etc. This article mainly focuses on the latter and briefly introduces some recent developments in EDA technology and its applications.
Due to its obvious advantages in the field of electronic system design, EDA technology and its applications based on large-scale programmable device solutions have made great progress in recent years, pushing electronic design technology to a new historical stage again. These new developments generally include the following 6 aspects: ① New devices; ② New tool software; ③ Embedded system design; ④ DSP system design; ⑤ Computer processor design; ⑥ Competitive technology with the ASIC market. The following will explain them separately.
1. New devices
Due to the market demand for products and the promotion of market competition, new devices that can be supported by mature EDA tools and that also represent the latest EDA technology development results are constantly emerging. Their main characteristics are:
(1) Large scale. The logic scale has reached millions of gates and nearly 100,000 logic macro units. A complex circuit system, including one or more embedded system processors, various communication interfaces, control modules and DSP modules, can be installed in one chip, which can meet the so-called SOPC design. Typical devices include Altera's Stratix series and Excalibue series; Xilinx's Virtex-II Pro series and Spartan-3 series (this series has reached 90nm process technology).
(2) Low power consumption. Although general FPGAs and CPLDs can meet most system design requirements in terms of function and scale, they are usually difficult to meet the requirements of portable products with low power consumption requirements. However, the ispMACH4000z series CPLDs newly launched by Lattice have achieved unprecedented low power performance, with a static power consumption of 20 microamperes, so it is called a 0-power device, while other performance, such as speed, scale, interface characteristics, etc., still maintain good indicators.
(3) Analog programmable. Various analog programmable and analog-to-digital mixed programmable devices designed by EDA tools and software and programmed and downloaded in the isp mode continue to appear. The most representative device is Lattice's ispPAC series devices, including conventional analog programmable devices ispPAC10; precision high-order low-pass filter design dedicated device ispPAC80; analog-to-digital mixed general-purpose in-system programmable device ispPAC20; in-system programmable electronic system power management device ispPAC-POWER, etc.
(4) FPGAs with multiple dedicated ports and additional functional modules. For example, Lattice's ORT and ORSO series devices, FPGAs with sysHSI SERDES technology, have SERDES backplane transceivers with communication speeds up to 3.7Gbps, embedded 8b/10b codecs, and more than 400,000 gates of FPGA programmable logic resources; Altera's Stratix, Cyclone, APEX and other series devices, in addition to a large number of embedded ESBs (embedded system blocks), also contain embedded phase-locked loop modules (for clock generation and management), embedded microprocessor cores, etc. In addition, Stratix series devices are also embedded with a wealth of DSP modules.
2. New tool software
In order to adapt to the development of larger-scale FPGAs, including the development of DSPs for system-on-chips, in addition to the general EDA tools that are constantly updated by third-party EDA companies, major PLD suppliers have also launched and upgraded their EDA development tools in a timely manner.
For example, Lattice upgraded from the early Synario to the later ispEXPERT System, ispDesignEXPERT System, ispLEVER, and now ispLEVER Advanced System, a general EDA tool that can be used to develop all Lattice FPGA, FPSC, CPLD and GDX devices. The
latest design environment launched by Xilinx is ISE6.1I, which adds many new features, such as support for Linux development of embedded systems, support for mixed hardware description language integrated design flow, enhanced debugging function, Chip Scope Pro real-time debugger, etc. In addition, the Embedded Development Kit, a tool for debugging soft-core embedded systems, and the FPGA-based DSP development environment System Generator for DSP have also been upgraded.
Similarly, Altera has also launched EDA development environments suitable for different design objects. Among them, QuartusⅡ 3.0 is a comprehensive design environment, known as the SOPC (System on a Programmable Chip) upgrade environment. It inherits all the design functions and device objects of the original MaxplusⅡ and adds many new functions and new FPGA device series, including some large-scale devices suitable for SOPC development.
Compared with the above EDA tools, QuartusⅡ has many more distinctive and powerful practical functions, which are roughly as follows:
(1) QuartusⅡ is combined with MATLAB/Simulink and Altera's DSP Builder, as well as third-party synthesizers and simulators, to develop DSP hardware systems;
(2) QuartusⅡ is combined with SOPC Builder to develop Nios embedded systems;
(3) QuartusⅡ includes real-time debugging tools and embedded logic analyzer Signal TapⅡ.
With the increasing complexity of logic design, simulation testing in software on computers has become more time-consuming, and the repeated testing of hardware systems has also become more difficult. In order to solve these problems, designers can combine an efficient hardware real-time testing method with traditional system testing methods. This is the use of embedded logic analyzer Signal TapⅡ. It can be downloaded to the target chip along with the design file to capture the signals at the signal nodes of interest to the designer in the target chip without affecting the normal operation of the original hardware system. There are two ways to use Signal TapⅡ. One is to use Signal TapⅡ in QuartusⅡ3.0 directly. The other is to use Signal TapⅡ through MATLAB's Simulink and DSP Builder. DSP Builder contains the Signal TapⅡ module. Designers can use this module to set event triggers for signal detection, configure memory, and display waveforms. This can use the Node module to select the signal to be monitored. After using Signal TapⅡ, when the trigger runs, it usually takes up part of the internal RAM, because in actual monitoring, the measured sample signal is temporarily stored in the embedded RAM (such as ESB) in the target device, and then the collected information is transmitted through the device's JTAG port and Byte BlasterⅡ download line to the PC for analysis. The data sent to the PC is stored in the form of a text file, and the waveform can be displayed on the Simulink diagram;
(4) QuartusⅡ contains a very effective logic design optimization technology, that is, the logic locking function of the design module in the specified area in the FPGA, the Logic Lock technology.
有FPGA开发经验的人都会有这样的体会，原来在硬件测试上十分成功的FPGA设计，结果在源代码并没有任何改变的情况下，仅仅是增加了一点与原程序毫不相干的电路描述，或甚至只改变了某个端口信号的引脚锁定位置，结果在综合适配后，原设计的硬件性能大为下降，如速度降低了，有时甚至无法正常工作。这时，如果比较改变设计前后的Floorplan图，会发现芯片内部资源的使用情况发生了巨大的变化。这表明，即使对原设计作极小的改变（更不用说对适配约束条件的改变），都会使适配器对原设计的布线（routing）和布局（placing）策略作大幅改变和调整。同时，当设计规模比较大时，人为很难直接介入布线/布局的优化。对于由许多基本电路模块构建成的顶层系统的FPGA开发，类似的问题将更加突出。例如，原来某一基本模块的FPGA硬件测试十分成功，包括工作性能、速度以及资源利用率等，但当将这些基本模块连接到一个顶层设计后，即使在同一FPGA中进行测试，也常发现各模块以及总系统的性能有所下降，甚至无法工作的情况。事实上，如果能在设计基本模块时，就固定其布线/布局的原方案，即使在顶层文件的总体适配时，也不改变原来基本模块的布线/布局及其原来的优化方案，就能很好地解决上述棘手的问题。对此，QuartusⅡ提供了这一优秀的设计技术，可以将设计好的布线/布局方案。这样一来，对于一项较大设计中的某一底层模块，不但在顶层的软件描述上是一个子模块，而且在FPGA芯片中总体适配中，此模块在硬件便类似于ASIC设计中的一个标准模块，始终能保持自己原来的布线/布局方案，从而在任何大系统中都能保持原有的电路性能，就像一个被调用的独立的元件一样，不会由于顶层系统布线/布局的改变而改变基本模块的布线/布局结构了。有了逻辑锁定技术，面对大系统的设计，工程师们就可以将构成大系统的各模块进行分别设计，分别优化它们的布线/布局，及适配约束，逐个地使它们分别获得最佳的工作性能，逐个优化交锁定它们的布线/布局方案，最后把它们连在一起形成性能优良的顶层系统。显然，逻辑设计锁定技术是SOPC单片系统优化设计及IP核成功拼装应用的有力保证。
（5）QuartusⅡ含有将FPGA设计向ASIC设计我缝转移的高效的ASIC设计技术，即Hard Copy技术，对此将在后面做更多的说明。
3、在FPGA中植入嵌入式系统处理器
目前最为常用的嵌入式系统大多采用了含有ARM的32位知识产权处理器核的器件。尽管由这些器件构成的嵌入式系统有很强的功能，但为了使系统更为完备、功能更为强大、对更多任务的完成具有更好的适就万籁 ，通常必须为此处理器配置许多接口器件，方能构成一个完整的应用系统，如除配置常规的SRAM、DRAM、Flash外，还必须配置网络通信接口、串行通信接口USB接口、VGA接口、PS/2接口等等。这样势必会增加整个系统的体积、功耗，降低了系统的可靠性。但是如果将ARM或其它知识产权核以硬核方式植入FPGA中，利用FPGA中的可编程逻辑资源和IP软核来构成该嵌入式系统处理器的接口功能模块，就能很好地解决这些问题。对此，Altera和Xilinx公司都相继推出了这方面的器件。例如，Altera的Excalibur系列FPGA中就植入了ARM922T嵌入式系统处理器；Xilinx的Virtex-ⅡPro系列中植入了IBM PowerPC405处理器。这样就能使得FPGA的强大的软件功能有机地相结合，高效地实现SOC系统。
但是，这种将IP硬核植入FPGA的解决方案存在5种不够完美之处：
（1）由于此类硬核多来自第三方公司，FPGA厂商通常无法直接控制其知识产权费用，从而导致FPGA器件价格相对较高；
（2）由于硬核是预先植入的，设计者无法根据实际需要改变处理器的结构，如总线规模、接口方式，乃至指令形式，更不可能将FPGA逻辑资源构成的硬件模块以指令的形式形成内置嵌入式系统的硬件加速模块（如DSP模块），以适应更多的电路功能要求；
（3）无法根据实际设计需求在同一FPGA中使用指定数量的处理器核；
（4）无法裁减处理器硬件资源以降低FPGA成本；
（5）只能在特定的FPGA中使用硬核嵌入式系统，如只能使用Excalibur系列FPGA中的ARM核，Virtex-ⅡPro系列中的PowerPC核。
但是如果利用软核嵌入式系统处理器就能有效地解决上述不利因素。它们分别是Altera的Nios核与Xilinx的Micro Blaze。特别是前者，使上述5方面的问题得到全面的解决。
Altera的Nios核是用户可随意配置和构建的32位/16位总线（用户可选的）指令集和数据通道的嵌入式系统微处理器IP核，采用Avalon总线结构通信接口，带有增强的内存、调试和软件功能（C或汇偏程序程序优化开发功能）；含由First Silicon Solutions（FS2）开发的基于JTAG的片内设备（OCI）内核（这为开发者提供了强大的软硬件调试实时代码，OCI调试功能可根据FPGA JTAG端口上接受的指令，直接监视和控制片内处理器的工作情况）。
此外，基于QuartusⅡ平台的用户可编辑的Nios核含有许多可配置的接口模块核，包括：可配置高速缓存（包括由片内ESB或外部SRAM或SDRAM，100M以上单周期访问速度）模块，可配置RS232通信口、SDRAM控制器、标准以太网协议接口、DMA、定时器、协处理器等等。在植入（配置进）FPGA前，用户可根据设计要求，利用QuartusⅡ和SOPC Builder，对Nios及其外围系统进行构建，使该嵌入式系统在硬件结构、功能特点、资源占有等方面全面满足用户系统设计的要求。Nios核在同一FPGA中被植入的数量没有限制，只要FPGA的资源允许，此外Nios可植入的Altera FPGA的系列几乎没有限制，在这方面，Nios显然优于Xilinx的Micro Blaze。
另外，在开发工具的完备性方面、对常用的嵌入式操作系统支持方面，Nios都优于Micro Blaze。就成本而言，由于Nios是由Altera直接推出而非第三方产品，故用户通常无需支付知识产权费用，Nios的使用费仅仅是其占用的FPGA的逻辑资源费。因此，选用的FPGA越便宜，则Nios的使用费就越便宜。
4、基于FPGA的DSP系统设计
在这去很长一段时间内，DSP处理器（如T1的TMS320系列）是DSP应用系统核心器件的唯一选择。尽管DSP处理器具有通过软件设计能适用于不同功能实现的灵活性，但面对当今迅速变化的DSP应用市场，特别是面对现代能信技术的发展，早已显得力不从心了。
For example, the immutability of its hardware structure leads to the immutability of its bus, and the fixed data bus width has become a bottleneck that is difficult to break through for DSP processors. This fixed hardware structure of DSP processors is particularly unsuitable for many current applications that require the ability to change structural characteristics at any time, namely the so-called user-oriented DSP system, or user-customizable (such as DSP system using DSP hard-core acceleration module composed of Nios plus FPGA resources), or reconfigurable DSP application system (Customized DSP or Reconfigurable DSP, etc., i.e. DSP system using the reconfigurable characteristics of FPGA), such as software radio, medical equipment, navigation, industrial control, etc. As for meeting speed requirements, due to the use of sequential execution CPU architecture, DSP processors are even more overwhelmed.
Although various dedicated ASIC chips for DSP can solve the problems of parallelism and speed, the high development and design costs, time-consuming design cycle and inflexible pure hardware structure make DSP ASIC solutions increasingly lose their practicality.
The emergence of modern large-capacity and high-speed FPGAs has overcome many of the shortcomings of the above solutions. These FPGAs are generally embedded with configurable high-speed RAM, PLL, LVDS, LVTTL, hardware multiplier and accumulator and other DSP modules. Using FPGA to implement digital signal processing can solve the problems of parallelism and speed, and its flexible configurable characteristics make the DSP system composed of FPGA very easy to modify, test and upgrade the hardware.
In the development and application of DSP systems using FPGA, there are new design tools and design processes. DSP Builder is a system-level tool for DSP development launched by Altera. It appears as a Simulink toolbox (Tool Box) of Matlab. Matlab is a powerful mathematical analysis tool, widely used in scientific computing and engineering computing, and can model, estimate parameters and analyze performance of complex digital signal processing systems. Simulink is a component of Matlab, which is used for graphical modeling and simulation.
As a toolbox in Simulink, DSP Builder makes it possible to design DSP systems using FPGA through the graphical interface of Simulink, just by simply calling the modules in the DSP Builder toolbox. It is worth noting that the DSP basic modules in DSP Builder are described at the algorithm level, which is easy for users to understand from the system or algorithm level, and they do not even need to fully understand FPGA itself and hardware description language.
In contrast, the problems of commonly used digital signal processing (DSP) solutions are:
(1) Slow working speed. For example, the processing speed of TMS320C5402/10/16 is only 0.1GMACs, and the working speed of A/D and D/A on the related "DSP Experiment Development System" is only 40kHz, which is in the voice frequency range. The sampling and output frequency range of the signal are relatively low, and very few experimental projects can be completed. Most experiments in the communication field cannot be completed (such as DDS, FSK, etc.). The DSP processing speed of the FPGA system can reach 70GMACs, and the working speed of the related A/D and D/A can reach tens to hundreds of MHz, which can reach the radio frequency range.
(2) It will be powerless in the field of digital communication, such as software radio.
(3) Since the system is completely based on a specific DSP processor, the hardware system cannot be reconfigured in real time or non-real time for requirements such as protocol updates, communication format changes, and hardware working mode changes. FPGA has a reconfiguration function, which is very easy to achieve.
(4) Although JTAG debugging is used, the traditional CPU debugging method is still used in essence. For many different DSP devices, different hardware structures, assembly languages and development tools will correspond to different hardware structures. Therefore, the development and design technology is difficult to standardize and normalize, and the development efficiency is extremely low.
(5) It is difficult to incorporate advanced SOC development technology and related top-down system-level design and optimization.
(6) Developers can only passively follow and use existing DSP devices on the market, and cannot design their own DSP hardware system based on the technical indicators, structural characteristics, future hardware upgrade possibilities, cost-effectiveness estimation and other necessary factors of the established design system.
However, modern DSP technology based on FPGA and SOPC technology has completely broken through the bottleneck of traditional DSP systems and design technologies, overcome many disadvantages of traditional solutions, and expanded its own new space in the field of high-frequency and high-speed DSP design and application. Modern DSP solutions are completely based on EDA's unique top-down design process and high-speed parallel algorithm structure.
The design method can start from the system level which is completely unrelated to the hardware. First, the top-level system design and system simulation test are completed by using the powerful system design and analysis capabilities of Matlab and the modules (or IP cores) provided by DSP Builder. Then, the Simu link model file is automatically converted into the RTL expression of VHDL and the tool command language (Tcl) script through the Signal Compiler in DSP Builder. Then, the functional simulation at the RTL level is performed, and the synthesis, adaptation and timing simulation are performed through the SOPC design tool QuartusⅡ. Finally, the POF and SOF files for programming and configuring the specified FPGA are formed to realize the simulation test of the hardware DSP system. During this period, the set embedded logic analyzer Signal TapⅡDSP hardware system file can be adapted and downloaded to the FPGA chip. Then, the real-time working waveform of the DSP hardware module in the chip measured by Signal TapⅡ through the JTAG port can be observed in the Simu link window of MATAB, thereby realizing the purpose of hardware simulation and debugging. Finally, if necessary, the DSP hardware module can be edited into the user instructions of the Nios embedded system processor through the SOPC interface. Obviously, this advanced design technology has finally made DSP technology embark on the path of standardization, standardization, high efficiency and intellectual property rights in high-frequency digital signal processing.
5.
The success of EDA technology and FPGA in the field of communication is a well-known fact, and the implementation of general processors is also commonplace. For example, hardware description language is used to design embedded system processors, various CPUs or single-chip microcomputers, etc., and they are implemented in FPGA in the form of soft cores. However, using FPGA to realize high-performance processors and even the functions of supercomputer processors cannot but be said to be a brand-new attempt. At present, although the FPGA implementation of computer processors based on EDA technology has not yet entered the stage of comprehensive commercial development, its research and application results have to make people deeply feel the huge potential and broad market of FPGA in this field.
For example, the processor in a server that Wincom Systems is launching is actually designed with Xilinx's FPGA. This server designed for website operation is only the size of a DVD player, but its working capacity is equivalent to or even exceeds 50 Dell, IBM or SUN servers priced at $5,000, and its cost is only $25,000. We know that traditional personal computers and servers usually use Intel's Pentium processor or SUN Computer System's SPARC chip as the central processing unit, but Wincom Systems' product does not use traditional microprocessors, but uses field programmable gate array (FPGA) chips to drive it. Although the main frequency of FPGA chips is slower than that of Pentium processors, they can complete multiple tasks in parallel, that is, the microprocessor can only execute one instruction and complete one operation in each time beat (such as a certain instruction cycle). Therefore, Wincom Systems' servers only need to be equipped with a few FPGA chips priced at only more than $2,000 to beat SUN's servers or computers using Intel processors, achieving what Douglas Henderson, the company's vice president, said, that its server processing speed is 50 to 300 times faster than ordinary servers.
In addition, Time Logic in the United States has also indirectly benefited from FPGA chips. Some standard servers produced by Dell and SUN also use Altera's FPGA chips. Time Logic has improved these standard servers and produced a high-speed processing device for genetic research. Christopher Hoover, the company's director, said that their equipment is at least 1,000 times faster than the original product! Annapolis Micro Systems has also integrated Xilinx's FPGA chips in its computer circuit boards to improve product performance. Although the average selling price of this product is as high as $25,000, its sales volume has doubled compared to before. Blue Arc in the United States has used FPGA to develop a memory product with faster access speed than competing products from Network Appliance and EMC. Mid Stream Technologies uses FPGA chips to develop video streaming servers for cable TV operators. This server uses 2 FPGA chips and can provide 425 video streaming signals at the same time, which is much faster than servers based on general-purpose microprocessors.
Especially when using FPGAs embedded with powerful microprocessors (such as Virtex-Ⅱ Pro) to build processors in servers, the system has great hardware design flexibility. For example, the programmable logic in the FPGA of a network server can be customized according to different standards without having to develop a new chip for each country.
It goes without saying that with the help of powerful EDA tools, FPGA-based processors are eating into the microprocessor market to a certain extent. More than 50 years ago, Hungarian mathematician Neumann proposed the design concept of a computer, which is to access data from memory through a central processing unit and handle each task one by one. Now, by replacing microprocessors with programmable chips, computers can handle multiple tasks in parallel, changing the basic working method of the computer architecture proposed by Neumann, thus opening up a new path for the computer design field to break through the traditional microprocessor that has reached its speed limit. At the same time, as Xilinx CEO Willem Roelandts said, "Programmable chips will set off the next round of application climax."
Processors implemented with FPGAs based on EDA development technology will also have a place in the design of supercomputers. Traditional supercomputers should be the best in the world of science and technology. They are extremely expensive and fast, and they integrate thousands of microprocessors. But this kind of supercomputer also wastes a lot of chip resources. Each processor can only perform single-task operations, and most functions are difficult to fully utilize. If FPGA is used to equip supercomputers, on the basis of giving full play to the original parallel work of FPGA, the reconfigurable characteristics of FPGA are utilized, that is, for different processing tasks and algorithm models, the corresponding processor structure files of FPGA are configured on site, so that the same hardware circuit structure can form different equivalent hardware structures in different time periods to efficiently deal with different processing tasks. For example, this supercomputer can be used to forecast global weather conditions at a certain moment, and can be used to assess the risk of the bond market based on the main interest rate hedging situation of a certain company at the next moment, and then enter the analysis of gene combination verification, etc.
Therefore, it is not difficult to understand that, as Roelandts said, "We believe that the next generation of supercomputers will be based on programmable logic devices." He claimed that the functions of such machines will be much more powerful than the largest supercomputers currently available. EDA expert William Carter believes that as long as the functions of EDA development tools allow, there will be countless evidences to prove that FPGA has this magical ability, thereby realizing the development of supercomputers based on FPGA.
Star Bridge Systems, a US company, claims to have solved this problem. The system company used FPGA chips and the company's own Viva programming language to develop a "hypercomputer" with "unparalleled running speed." Scientists from the National Aeronautics and Space Administration (NASA) who tested the supercomputer said that the performance of this product is impressive, but it has not yet reached the practical stage. Researchers from other companies or institutions, such as researchers from the University of California, Berkeley and Brigham Young University, are also designing FPGA-based supercomputers that can be dynamically (on-site) reconfigured during operation. This is very useful for military applications such as locating dangerous targets and computationally intensive security applications such as facial recognition, which require multi-tasking functions with different hardware acceleration algorithms.
6. Competitive technology with the ASIC market
Although EDA technology development targets ASIC and FPGA, the comparison of their advantages and disadvantages in the application field has always been very clear. However, in recent years, with the continuous enhancement of EDA development tool functions and the improvement of FPGA device performance, this comparison is becoming blurred in many aspects.
On the one hand, the emergence of competitive FPGA devices has made the disadvantages of FPGA in terms of single-chip cost, logic scale and working speed smaller and smaller than ASIC. Its great flexibility, on-site configurability (equivalent to on-site hardware upgrade or hardware reconstruction), good design efficiency and success rate have continuously strengthened the position of FPGA as a competitor in the ASIC market. The Cyclone series FPGA launched by Altera and the Spartan-3 series FPGA launched by Xilinx are both representatives of such large-scale programmable devices. Of course, this is only an indirect competition and substitution.
On the other hand, by strengthening the design capabilities of EDA tools, while maintaining the advantages of FPGA development, the development process of ASIC is introduced, thus forming direct competition with the ASIC market. This is the HardCopy technology launched by Altera.
HardCopy is to use the original FPGA development tools to directly transform the system successfully implemented on the FPGA device into ASIC through specific technology, thereby overcoming the common problems in traditional ASIC design.
Compared with HardCopy technology, there are many difficult problems to overcome for large-scale ASIC development at the system level, including long development cycle, slow product launch, low one-time success rate, minimum wafer volume requirements, numerous and expensive design software tools, and complex development process. For example, this type of ASIC development first requires a considerable team of technicians, hundreds of thousands of dollars in development software costs, and high mask costs, and the entire design cycle may be as long as one year. The high cost and low one-time success rate of ASIC design are largely due to the large number of layers that need to be designed and masked (up to a dozen layers).
However, if HardCopy technology is used to design ASIC, the software development cost is only $2,000 (QuartusⅡ), the design cycle of SOC-level scale does not exceed 20 weeks, the converted ASIC has only two mask layers with the user's design habits, and the success rate of one-time wafer casting is nearly 100%, which is the so-called seamless conversion from FPGA to ASIC. Moreover, the system performance after ASIC implementation will be nearly 50% higher than the model previously verified on HardCopy FPGA, while the power consumption will be reduced by 40%. The significant improvement in the one-time success rate means a significant reduction in design costs and a significant increase in the speed of product launch.
HardCopy technology is a brand-new ASIC design solution, which combines dedicated silicon chip design and FPGA to HardCopy automatic migration process. That is, first use QuartusⅡ to successfully implement the system model on HardCopy FPGA, and then help design a solution that seamlessly migrates the programmable solution to a low-cost ASIC. In this way, HardCopy devices combine the flexibility of large-capacity FPGAs with the market advantages of ASICs to achieve electronic system products with large-volume requirements and cost sensitivity. Thus, the difficulty of directly designing ASIC is avoided, and the design of FPGA can be easily transplanted to HardCopy devices from prototype design to product manufacturing, so as to reduce costs and speed up the time to market. HardCopy devices (such as HardCopy Stratix series and Excalibur series FPGA) avoid the risks of ASIC and use FPGA's dedicated migration technology. Its HardCopy ASIC is built directly on the Altera PLD system, using the "logic unit sea" core that effectively utilizes the area. In essence, HardCopy devices are accurate copies of FPGAs, eliminating programmability, dedicated configuration and routing used for metal interconnection. In this way, the silicon area of the device is smaller, the cost is lower, and the timing characteristics are improved.
Since EDA technology is a technology aimed at solving the most basic and lowest-level hardware implementation problems of electronic systems, its development trend is bound to involve more and more broad electronic technology and electronic design technology fields. These include electronic engineering, electronic information, communications, aerospace, industrial automation, home appliances, bioengineering, etc. Moreover, with the development of large-scale integrated circuit technology and the continuous enhancement of EDA tool software functions, the fields involved will continue to expand; and from a vertical perspective, the hardware form of EDA technology and the theoretical models involved will inevitably move towards a unified combination, namely single-chip system SOC or SOPC. ( http://www.newmaker.com ) |
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