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Chapter 1 PCB Layout In PCB design, wiring is an important step to complete product design. It can be said that the previous preparations are all done for it. In the entire PCB , the design process of wiring is the most demanding, the most skillful, and the most labor-intensive. PCB wiring includes single-sided wiring, double-sided wiring, and multi-layer wiring. There are also two ways of wiring: automatic wiring and interactive wiring. Before automatic wiring, you can use interactive wiring to pre-wire the lines with stricter requirements. The edge lines of the input and output ends should avoid adjacent parallel lines to avoid reflection interference. If necessary, ground wire isolation should be added. The wiring of two adjacent layers should be perpendicular to each other. Parallel wiring is prone to parasitic coupling. The routing rate of automatic wiring depends on a good layout. The wiring rules can be pre-set, including the number of bends in the routing, the number of vias, the number of steps, etc. Generally, exploratory wiring is performed first to quickly connect the short lines, and then maze wiring is performed. The wiring path of the connection to be routed is optimized globally. It can disconnect the routed lines as needed. And try to re-route to improve the overall effect. The through hole is not suitable for the current high-density PCB design. It wastes a lot of precious wiring channels. To solve this contradiction, blind hole and buried hole technology have emerged. It not only completes the function of the through hole, but also saves a lot of wiring channels to make the wiring process more convenient, smoother and more perfect. The design process of the PCB board is a complex and simple process. In order to master it well, it is necessary for the majority of electronic engineering designers to experience it by themselves to get the true meaning. 1. The treatment of power and ground wires . Even if the wiring in the entire PCB board is completed well, the interference caused by the lack of consideration of the power and ground wires will reduce the performance of the product and sometimes even affect the success rate of the product. Therefore, the wiring of the power and ground wires should be taken seriously, and the noise interference generated by the power and ground wires should be reduced to a minimum to ensure the quality of the product. Every engineer engaged in the design of electronic products understands the cause of the noise between the ground wire and the power wire. Now we will only describe the noise reduction method: 4 ( 1 ) It is well known that decoupling capacitors are added between the power and ground wires. ( 2 ) Try to widen the width of the power supply and ground wires. It is best that the ground wire is wider than the power supply wire. The relationship between them is: ground wire > power supply wire > signal wire. Usually the signal wire width is: 0.2 ~ 0.3mm, the thinnest width can reach 0.05 ~ 0.07mm, and the power wire is 1.2 ~ 2.5mm. For the PCB of digital circuits, a wide ground wire can be used to form a loop , that is, to form a ground network for use ( the ground of analog circuits cannot be used in this way ) ( 3 ) Use a large area of copper layer as a ground wire , and connect all unused areas on the printed circuit board to the ground as a ground wire. Or make a multi-layer board, with the power supply and ground wire occupying one layer each.
2. Common ground processing of digital circuits and analog circuits Now many PCBs are no longer single-function circuits (digital or analog circuits), but are composed of a mixture of digital circuits and analog circuits. Therefore, when wiring, it is necessary to consider the mutual interference between them, especially the noise interference on the ground line. The frequency of digital circuits is high, and the sensitivity of analog circuits is strong. For signal lines, high-frequency signal lines should be as far away from sensitive analog circuit devices as possible. For ground lines, the entire PCB has only one node to the outside world, so the problem of digital and analog common ground must be processed inside the PCB . In fact, the digital ground and analog ground are separated inside the board. They are not connected to each other, but at the interface where the PCB is connected to the outside world (such as plugs, etc.). There is a short circuit between the digital ground and the analog ground. Please note that there is only one connection point. There are also non-common grounds on the PCB , which is determined by the system design. 3. Signal lines are laid on the power (ground) layer . When wiring a multi-layer printed circuit board, there are not many lines left in the signal line layer. Adding more layers will cause waste and increase the workload of production. The cost will also increase accordingly. To solve this contradiction, you can consider wiring on the power (ground) layer. First, consider using the power layer, and then the ground layer. Because it is best to preserve the integrity of the ground layer.
4. Treatment of connecting legs in large-area conductors In large-area grounding (electricity), the legs of common components are connected to it. The treatment of connecting legs needs to be comprehensively considered. In terms of electrical performance, it is better for the pads of the component legs to be fully connected to the copper surface, but there are some bad hidden dangers for the welding and assembly of components, such as: ① Welding requires a high-power heater. ② It is easy to cause cold solder joints. Therefore, taking into account both electrical performance and process requirements, a cross-shaped pad is made, which is called heat shield, commonly known as thermal pad . In this way, the possibility of cold solder joints caused by excessive heat dissipation in the cross section during welding can be greatly reduced. The treatment of the connecting (ground) layer legs of multi-layer boards is the same. 5. The role of the network system in wiring In many CAD systems, wiring is determined by the network system. The grid is too dense, and although the passages have increased, the step is too small, and the amount of data in the drawing field is too large, which will inevitably have higher requirements for the storage space of the equipment, and also have a great impact on the computing speed of computer-related electronic products. Some paths are invalid, such as those occupied by the pads of the component legs or by the mounting holes and fixed holes. Too sparse grids and too few paths have a great impact on the routing rate. Therefore, a grid system with reasonable density is required to support the routing. The distance between the two legs of a standard component is 0.1 inches (2.54 mm), so the basis of the grid system is generally set to 0.1 inches (2.54 mm) or an integer multiple of less than 0.1 inches, such as: 0.05 inches, 0.025 inches, 0.02 inches, etc. 6 Design Rule Check ( DRC ) After the routing design is completed, it is necessary to carefully check whether the routing design complies with the rules set by the designer, and also to confirm whether the rules set meet the requirements of the printed circuit board production process. The general inspection includes the following aspects: ( 1 ) Whether the distance between lines, lines and component pads, lines and through holes, component pads and through holes, and through holes is reasonable and meets the production requirements. ( 2 ) Are the widths of the power and ground lines appropriate? Are the power and ground lines tightly coupled (low wave impedance)? Are there any places in the PCB where the ground line can be widened? ( 3 ) Have the best measures been taken for key signal lines, such as the shortest length, adding protection lines, and clearly separating the input and output lines? ( 4 ) Do the analog and digital circuits have their own independent ground lines? ( 5 ) Will the graphics (such as icons and annotations) added to the PCB later cause signal short circuits? ( 6 ) Modify some undesirable line shapes. ( 7 ) Are there process lines added to the PCB ? Does the solder mask meet the requirements of the production process? Is the solder mask size appropriate? Is the character mark pressed on the device pad to avoid affecting the quality of the electrical equipment? ( 8 ) Is the outer frame edge of the power ground layer in the multilayer board reduced? If the copper foil of the power ground layer is exposed outside the board, it is easy to cause a short circuit.
Part 2 PCB Layout In design, layout is an important link. The quality of layout results will directly affect the effect of wiring. Therefore, it can be considered that reasonable layout is the first step to the success of PCB design. There are two ways of layout, one is interactive layout and the other is automatic layout. Generally, interactive layout is used for adjustment based on automatic layout. During layout, gate circuits can be redistributed according to the routing situation, and two gate circuits can be exchanged to make it the best layout for easy wiring. After the layout is completed, the design files and related information can be returned and marked on the schematic diagram, so that the relevant information in the PCB board is consistent with the schematic diagram, so that the relevant information in the future can be synchronized in the filing and design changes . At the same time, the relevant information of the simulation is updated, so that the electrical performance and function of the circuit can be verified at the board level. --Consider the overall aesthetics . The success of a product depends on the internal quality and the overall aesthetics. Only when both are perfect can the product be considered successful. On a PCB board, the layout of components must be balanced, dense and orderly, and cannot be top-heavy or heavy. --Layout inspection . Does the size of the printed board match the size of the processing drawing? Can it meet the requirements of the PCB manufacturing process? Are there any positioning marks? Are there any conflicts between components in two-dimensional and three-dimensional space? Are the components arranged in an orderly and orderly manner? Are all the components arranged? Can the components that need to be replaced frequently be replaced easily? Is it convenient to insert the plug-in board into the device? Is there an appropriate distance between the thermistor and the heating element? Is it convenient to adjust the adjustable components? Are heat sinks installed where heat dissipation is required? Is the air flow unobstructed? Is the signal flow smooth and the interconnection is as short as possible? Are the plugs, sockets, etc. inconsistent with the mechanical design? Have the interference problems of the lines been considered?
Part 3 High-Speed PCB Design 1. Challenges faced by electronic system design With the large-scale increase in the complexity and integration of system design, electronic system designers are engaged in circuit design above 100MHZ , and the operating frequency of the bus has reached or exceeded 50MHZ , and some even exceed 100MHZ . At present, about 50% of the designs have a clock frequency exceeding 50MHz , and nearly 20% of the designs have a main frequency exceeding 120MHz . When the system operates at 50MHz , transmission line effects and signal integrity problems will occur; and when the system clock reaches 120MHz , unless high-speed circuit design knowledge is used, the PCB designed based on traditional methods will not work. Therefore, high-speed circuit design technology has become a design method that electronic system designers must adopt. Only by using the design technology of high-speed circuit designers can the controllability of the design process be achieved. 2. What is a high-speed circuit? It is generally believed that if the frequency of a digital logic circuit reaches or exceeds 45MHZ~50MHZ , and the circuit operating above this frequency has accounted for a certain proportion of the entire electronic system (for example, 1/3), it is called a high-speed circuit. In fact, the harmonic frequency of the signal edge is higher than the frequency of the signal itself. It is the rising and falling edges (or signal jumps) of the signal that change rapidly that cause the unexpected results of signal transmission. Therefore, it is usually agreed that if the line propagation delay is greater than 1/2 of the rise time of the digital signal driver, such a signal is considered to be a high-speed signal and produces a transmission line effect. The transmission of the signal occurs at the moment when the signal state changes, such as the rise or fall time. The signal travels from the driver to the receiver for a fixed period of time. If the transmission time is less than 1/2 of the rise or fall time, the reflected signal from the receiver will reach the driver before the signal changes state. On the contrary, the reflected signal will reach the driver after the signal changes state. If the reflected signal is very strong, the superimposed waveform may change the logic state. (III) Determination of high-speed signals Above we defined the prerequisites for the occurrence of transmission line effects, but how do we know whether the line delay is greater than 1/2 of the signal rise time at the driver? Generally, the typical value of the signal rise time can be given by the device manual, and the signal propagation time is determined by the actual wiring length in PCB design. The following figure shows the corresponding relationship between the signal rise time and the allowable wiring length ( delay ) . The delay per unit inch on the PCB board is 0.167ns . However, if there are many vias, many device pins, and many constraints set on the network line, the delay will increase. Usually the signal rise time of high-speed logic devices is about 0.2ns . If there is a GaAs chip on the board, the maximum wiring length is 7.62mm . Let Tr be the signal rise time and Tpd be the signal line propagation delay. If Tr≥4Tpd , the signal falls in the safe area. If 2Tpd≥Tr≥4Tpd , the signal falls in the uncertain area. If Tr≤2Tpd , the signal falls in the problem area. For signals that fall in the uncertain area and the problem area, high-speed wiring methods should be used. (IV) What is a transmission line? The traces on the PCB board can be equivalent to the series and parallel capacitor, resistor and inductor structures shown in the figure below. The typical value of the series resistor is 0.25-0.55 ohms/foot . Because of the insulation layer, the parallel resistor is usually very high. After adding parasitic resistance, capacitance and inductance to the actual PCB connection, the final impedance on the connection is called the characteristic impedance Zo . The wider the wire diameter, the closer to the power supply / ground, or the higher the dielectric constant of the isolation layer, the smaller the characteristic impedance. If the impedance of the transmission line and the receiving end do not match, the output current signal and the final stable state of the signal will be different, which will cause the signal to be reflected at the receiving end. This reflected signal will be transmitted back to the signal transmitting end and reflected back again. As the energy decreases, the amplitude of the reflected signal will decrease until the voltage and current of the signal reach stability. This effect is called oscillation, and the oscillation of the signal is often seen on the rising and falling edges of the signal.
（五）、传输线效应
基于上述定义的传输线模型，归纳起来，传输线会对整个电路设计带来以下效应。
· 反射信号Reflected signals
· 延时和时序错误Delay & Timing errors
· 多次跨越逻辑电平门限错误False Switching
· 过冲与下冲Overshoot/Undershoot
· 串扰Induced Noise (or crosstalk)
· 电磁辐射EMI radiation
5.1 反射信号
如果一根走线没有被正确终结(终端匹配)，那么来自于驱动端的信号脉冲在接收端被反射，从而引发不预期效应，使信号轮廓失真。当失真变形非常显著时可导致多种错误，引起设计失败。同时，失真变形的信号对噪声的敏感性增加了，也会引起设计失败。如果上述情况没有被足够考虑，EMI将显著增加，这就不单单影响自身设计结果，还会造成整个系统的失败。
反射信号产生的主要原因：过长的走线；未被匹配终结的传输线，过量电容或电感以及阻抗失配。
5.2 Delay and Timing Errors Signal delay and timing errors are manifested as: the signal does not jump for a period of time when it changes between the high and low thresholds of the logic level. Excessive signal delay may cause timing errors and confusion of device functions. Problems usually occur when there are multiple receiving ends. Circuit designers must determine the worst-case time delay to ensure the correctness of the design. Causes of signal delay: driver overload, long routing. 5.3 Multiple crossing of logic level threshold errors The signal may cross the logic level threshold multiple times during the transition process, resulting in this type of error. Multiple crossing of logic level threshold errors are a special form of signal oscillation, that is, the oscillation of the signal occurs near the logic level threshold. Multiple crossing of the logic level threshold will cause logic function disorder. Causes of reflected signals: too long routing, unterminated transmission lines, excessive capacitance or inductance, and impedance mismatch. 5.4 Overshoot and undershoot Overshoot and undershoot come from two reasons: too long routing or too fast signal changes. Although most components are protected by input protection diodes at the receiving end, sometimes these overshoot levels will far exceed the component power supply voltage range and damage the components. 5.5 Crosstalk Crosstalk is manifested as a signal passing through a signal line, and a related signal will be induced on the adjacent signal line on the PCB board, which we call crosstalk. The closer the signal line is to the ground line and the larger the line spacing, the smaller the crosstalk signal generated. Asynchronous signals and clock signals are more likely to generate crosstalk. Therefore, the method to resolve crosstalk is to remove the signal that causes crosstalk or shield the signal that is severely interfered. 5.6 Electromagnetic Radiation EMI (Electro-Magnetic Interference) is electromagnetic interference. The problems it causes include excessive electromagnetic radiation and sensitivity to electromagnetic radiation. EMI is manifested as the radiation of electromagnetic waves to the surrounding environment when the digital system is powered on, thereby interfering with the normal operation of electronic equipment in the surrounding environment. The main reason for its generation is that the circuit operating frequency is too high and the layout and wiring are unreasonable. At present, there are software tools for EMI simulation, but EMI simulators are very expensive, and it is difficult to set simulation parameters and boundary conditions, which will directly affect the accuracy and practicality of the simulation results. The most common approach is to apply various design rules for controlling EMI to every aspect of the design, thereby achieving rule-driven and control in each aspect of the design.
(VI) Methods to avoid transmission line effects In view of the effects introduced by the above transmission line problems, we will discuss methods to control these effects from the following aspects. 6.1 Strictly control the routing length of key network cables If there are high-speed transition edges in the design, it is necessary to consider the transmission line effect on the PCB board. The high-clock frequency fast integrated circuit chips commonly used now have such problems. There are some basic principles to solve this problem: If CMOS or TTL circuits are used for design, the operating frequency is less than 10MHz , and the wiring length should not exceed 7 inches. The wiring length should not exceed 1.5 inches at an operating frequency of 50MHz . If the operating frequency reaches or exceeds 75MHz, the wiring length should be 1 inch. For GaAs chips, the maximum wiring length should be 0.3 inches. If this standard is exceeded, there is a transmission line problem. 6.2 Reasonable planning of routing topology Another way to solve the transmission line effect is to choose the correct routing path and terminal topology. The routing topology refers to the routing sequence and routing structure of a network cable. When using high-speed logic devices, unless the routing branch length is kept very short, the signal with fast edge changes will be distorted by the branch routing on the signal trunk routing. Generally, PCB routing adopts two basic topologies, namely daisy chain routing and star distribution . For daisy chain routing, the routing starts from the driver end and reaches each receiving end in turn. If a series resistor is used to change the signal characteristics, the position of the series resistor should be close to the driver end. Daisy chain routing is the best in controlling the high-order harmonic interference of the routing. However, this routing method has the lowest routing rate and is not easy to be 100% routed. In actual design, we make the branch length in daisy chain routing as short as possible. The safe length value should be: Stub Delay <= Trt *0.1. For example, the branch end length in a high-speed TTL circuit should be less than 1.5 inches. This topology occupies less wiring space and can be terminated with a single resistor matching. However, this routing structure makes the reception of signals at different signal receiving ends asynchronous. The star topology can effectively avoid the problem of asynchronous clock signals, but it is very difficult to complete the routing manually on a high-density PCB board. Using an automatic router is the best way to complete star routing. Terminal resistors are required on each branch. The resistance of the terminal resistor should match the characteristic impedance of the connection. This can be calculated manually or by using a CAD tool to calculate the characteristic impedance value and the terminal matching resistor value. In the two examples above, simple terminal resistors are used. In practice, more complex matching terminals can be used. The first option is RC matching terminal. RC matching terminal can reduce power consumption, but can only be used when the signal is relatively stable. This method is most suitable for matching clock line signals. Its disadvantage is that the capacitor in the RC matching terminal may affect the shape and propagation speed of the signal. Series resistor matching terminal does not generate additional power consumption, but it will slow down the transmission of the signal. This method is used in bus driver circuits where time delay is not greatly affected. The advantage of series resistor matching terminal is that it can reduce the number of components used on the board and the connection density. The last method is separate matching terminal. In this way, the matching component needs to be placed near the receiving end. Its advantage is that it will not pull down the signal and can well avoid noise. It is typically used for TTL input signals (ACT, HCT, FAST) . In addition, the packaging type and mounting type of the terminal matching resistor must also be considered. Generally, SMD surface mount resistors have lower inductance than through-hole components, so SMD package components are the first choice. If you choose ordinary plug-in resistors, there are also two installation methods to choose from: vertical and horizontal. In the vertical installation method, one of the mounting pins of the resistor is very short, which can reduce the thermal resistance between the resistor and the circuit board, making it easier for the heat of the resistor to dissipate into the air. However, the longer vertical installation will increase the inductance of the resistor. The horizontal installation method has a lower inductance due to the lower installation. However, overheated resistors will drift, and in the worst case, the resistor will become an open circuit, causing the PCB trace termination matching to fail, becoming a potential failure factor. 6.3 Methods to suppress electromagnetic interference A good solution to the signal integrity problem will improve the electromagnetic compatibility (EMC) of the PCB board . It is very important to ensure that the PCB board has a good grounding. For complex designs, using a signal layer with a ground layer is a very effective method. In addition, minimizing the density of the outermost signal of the circuit board is also a good way to reduce electromagnetic radiation. This method can be achieved by using the " surface layer " technology "Build-up" design to make PCBs . Surface layering is achieved by adding a thin insulating layer and a combination of micro-holes that penetrate these layers on a common process PCB . Resistors and capacitors can be buried under the surface layer, and the wiring density per unit area will increase by nearly one-fold, thereby reducing the volume of the PCB . The reduction in PCB area has a huge impact on the topological structure of the wiring, which means a smaller current loop, a smaller branch wiring length, and electromagnetic radiation is approximately proportional to the area of the current loop; at the same time, the small volume feature means that high-density pin packaging devices can be used, which in turn reduces the length of the connection, thereby reducing the current loop and improving electromagnetic compatibility characteristics.
6.4 其它可采用技术
为减小集成电路芯片电源上的电压瞬时过冲，应该为集成电路芯片添加去耦电容。这可以有效去除电源上的毛刺的影响并减少在印制板上的电源环路的辐射。
当去耦电容直接连接在集成电路的电源管腿上而不是连接在电源层上时，其平滑毛刺的效果最好。这就是为什么有一些器件插座上带有去耦电容，而有的器件要求去耦电容距器件的距离要足够的小。
任何高速和高功耗的器件应尽量放置在一起以减少电源电压瞬时过冲。
如果没有电源层，那么长的电源连线会在信号和回路间形成环路，成为辐射源和易感应电路。
走线构成一个不穿过同一网线或其它走线的环路的情况称为开环。如果环路穿过同一网线其它走线则构成闭环。两种情况都会形成天线效应(线天线和环形天线)。天线对外产生EMI辐射，同时自身也是敏感电路。闭环是一个必须考虑的问题，因为它产生的辐射与闭环面积近似成正比。
结束语
高速电路设计是一个非常复杂的设计过程，ZUKEN公司的高速电路布线算法(Route Editor)和EMC/EMI分析软件(INCASES,Hot-Stage)应用于分析和发现问题。本文所阐述的方法就是专门针对解决这些高速电路设计问题的。此外，在进行高速电路设计时有多个因素需要加以考虑，这些因素有时互相对立。如高速器件布局时位置靠近，虽可以减少延时，但可能产生串扰和显著的热效应。因此在设计中，需权衡各因素，做出全面的折衷考虑；既满足设计要求，又降低设计复杂度。高速PCB设计手段的采用构成了设计过程的可控性，只有可控的，才是可靠的，也才能是成功的！
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