When using the GPIO port to simulate the IIC bus, should the input and output direction of the SDA port be set to input or output?

一沙一世

When using the GPIO port to simulate the IIC bus, should the input and output direction of the SDA port be set to input or output? [Copy link]

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When using the GPIO port to simulate the IIC bus, should the input and output direction of the SDA port be set to input or output?

shenyang_

SDA is used for both input and output. It is configured as output when sending data and as input when receiving data.

秦天qintian0303

The SDA port is set to input when inputting and output when outputting.

一沙一世

shenyang_ posted on 2023-8-12 15:20 SDA input and output will be used. When sending data, configure it as output, and when receiving data, configure it as input

ox!!!!!!

lkh747566933

The SDA pin of the IIC bus has both input and output. It is configured as output when sending data and as input when receiving data.

qwqwqw2088

SDA is a data line that is configured according to the SCL timing. There is no fixed
setting. How can it be set to input or output?

wangerxian

It is set as output at the beginning and as input when reading data.

damiaa

Depends on the timing regulations of I2C:

SCK is an output

SDA Sometimes input, sometimes output

For example, start stop bit

When ISCL is at a high level, SDA changes from high to low. This signal is the start signal .

ISCL is at a high level, and SDA changes from low to high. This signal is a stop signal. Output

Data sampling occurs during the SCL high level period. Except for the start and stop signals, during data transmission, when SCL is high level, SDA must remain stable and is not allowed to change. It can only change when SCL is low level. Output

Response: When the slave receives data from the host, it will reply with a response signal to inform the host that it has received the data.

The acknowledge signal appears after one byte is transmitted, that is, in the 9th SCL clock cycle. The host needs to release the SDA bus and give the bus control to the slave. Due to the pull-up resistor, the bus is high. If the slave correctly receives the data sent by the host, it will pull SDA low to indicate an acknowledge response .

No response signal

During the 9th SCL clock cycle, SDA remains at a high level, indicating a non-acknowledgement signal.

The non-response signal may be generated by the master or the slave .

voidp

IIC bus SDA bidirectional When data is sent, it is configured as output Configured as input when data is received