Tina Linux SPI master-slave communication verification based on Allwinner D1-H

aleksib

Tina Linux SPI master-slave communication verification based on Allwinner D1-H [Copy link]

 

> This article is reproduced from: [https://bbs.aw-ol.com/topic/3031](https://bbs.aw-ol.com/topic/3031) > Author @ whycan矿工-小叶## Background - Master: D1H - Board: Two Nezha development boards (hereinafter referred to as master and slave) - Operating system: Tina Linux 2.0 ## Problem verification D1H chip SPI master-slave communication. ## Hardware wiring | | Master SPI | Slave SPI | | | -- | --------- | --------- | -- | | 19 | SPI1_MOSI | SPI1_MOSI | 19 | | 21 | SPI1_MISO | SPI1_MISO | 21 | | 23 | SPI1_SCK | SPI1_SCK | 23 | | 24 | SPI1_CE | SPI1_CE | 24 | ## SPI Overview The SPI interface is a high-speed, Full-duplex, synchronous communication bus. The BSP-SDK (hereinafter referred to as SDK) of Tina Linux adapted to the D1H chip already contains the relevant driver file: spi-sunxi.c. It provides a simple communication verification experiment between the master and slave machines in kernel mode only, which may be due to the high communication rate of SPI. Verification operation## SPI host configuration### menuconfig After the SDK completes the environment variable loading, execute: ``` /mnt/tina-d1-h$ make kernel_menuconfig ``` ●Open Device Drivers->SPI support ●Enter SPI support and open it as shown in the figure:  ### Device tree modification: ./device/config/chips/d1-h/configs/nezha/board.dts  You need to confirm the pin function according to the manual and schematic diagram:  ## SPI slave configuration### menuconfig (same as SPI master configuration) ### Only spi_slave_mode is set to 0 in the device tree, and the rest of the items are consistent with the SPI master configuration. spi_slave_mode = <0>; ## SPI master sends and receives information according to the above configuration, recompiles the SDK, packages, burns, and starts the device, and the following will appear: ``` root@TinaLinux# ls -l /dev/spidev1.0 crw------- 1 root root 153, 0 Jan 1 08:00 /dev/spidev1.0 ``` Then move the executable SPI test program (./lichee/linux-5.4/tools/spi/spidev_test) to the device (adb push, etc.) and grant executable permissions: ``` # The host sends hexadecimal data at 10MHz (ie MOSI): 0x01 0x02 0x03 0x04 ./spidev_test -v -D /dev/spidev1.0 -s 10000000 -p "\x01\x02\x03\x04" # The host sends ASCII string data at 10MHz (ie MOSI): "allwinner" ./spidev_test -v -D /dev/spidev1.0 -s 10000000 -p "allwinner" spi mode: 0x0 bits per word: 8 max speed: 10000000 Hz (10000 KHz) TX | 61 6C 6C 77 69 6E 6E 65 72 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ |allwinner| ``` Note that SPI is a synchronous communication interface, so it will receive data of the same length while sending. The following article will use a common practice of SPI master-slave communication: the host sends the instruction header first, and then sends the instruction body to obtain the slave's response. ## SPI slave sends and receives information In spi-sunxi.c, a simple send and receive verification process is adopted for the SPI slave mode (SLAVE_MODE). Specifically, a kernel thread is created to execute int sunxi_spi_slave_task(void *data), This function is controlled by the device interrupt (when SPI data is received). - The main process of SPI slave receiving data: sunxi_spi_slave_task() -> sunxi_spi_slave_handle_head(), then: if the instruction header is a write operation (0x01), execute: sunxi_spi_slave_cpu_rx_config(), this function only outputs the write content. If the instruction header is a read operation (0x03), execute: sunxi_spi_slave_cpu_tx_config(), this function only adds 0x80 to the received instruction body value, and then sends (MISO) to the host. - For the slave, spi-sunxi.c can verify SPI communication, but there is no method that can be used directly by the user layer. ## User-level verifiable SPI slave transceiver solution### Functional design The slave arranges a 32-byte memory cache space (referred to as "cache space") for the host to perform read and write operations through instructions, And the slave can access this memory space at user level. ### Main changes - spi.c: - Add static struct class_attribute ye_spi_buf_attrs[] to create the spi_buf file in the /sys/class/spi_slave directory, and provide methods to implement read/write buffer space. - spi-sunxi.c: - Use ye_spi_slave_set_txdata() method to replace sunxi_spi_slave_set_txdata() to implement read operations. - Modify sunxi_spi_slave_cpu_rx_config() method to implement write operations. For details of the changes, please see: [d1h_spi_driver.diff](https://bbs.aw-ol.com/topic/3031/) ### Usage ``` Write operation: Operation: 0x01 (write) Address: 0x00 0x00 0x00 Instruction body length: 0x09 ./spidev_test -v -D /dev/spidev1.0 -s 10000000 -p "\x01\x00\x00\x00\x09" && \ .spidev_test -v -D /dev/spidev1.0 -s 10000000 -p "allwinner" Read operation: Operation: 0x03 (read) Address: 0x00 0x00 0x00 Instruction body length: 0x09 ./spidev_test -v -D /dev/spidev1.0 -s 10000000 -p "\x03\x00\x00\x00\x00\x09" && \ ./spidev_test -v -D /dev/spidev1.0 -s 10000000 -p "\x00\x00\x00\x00\x00\x00\x00\x00\x00" Slave reads cache space: cat /sys/class/spi_slave/spi_buf Slave writes cache space: echo "Hello world" > /sys/class/spi_slave/spi_buf ```

bigbat

Where is the SPI master-slave mode set? It would be nice if the key code of spidev_test can be analyzed.

bigbat

Is the detailed development information of this chip public?

freebsder

Thanks for sharing