Reading check-in station 8: memory barrier instructions, operating system - "RISC-V architecture programming and practice"

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Reading check-in station 8: memory barrier instructions, operating system - "RISC-V architecture programming and practice" [Copy link]

Activity details: Read "RISC-V Architecture Programming and Practice" together

This is the eighth stop for the reading and checking-in for "RISC-V Architecture Programming and Practice". Please reply to the author and ask the following questions.

Benshu helps you check in with your reading questions (reminder: read chapters 15, 16, and 17 of the book ):

34. What is the cause of memory disorder?
35. Please briefly describe the role and usage scenarios of the FENCE.I instruction and the SFENCE.VMA instruction.
36. What is process context switching? For RISC-V processors, what content needs to be saved for process context switching? Where is it saved?
37. Assuming that the scheduler switches process A to process B through the switch_to() function, does process B immediately execute the callback function of thread B after the switch is completed?

Friends who participated in the event, the reading check-in is about to end, let’s continue~

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34. What causes memory disorder?

____

If the actual memory access order of the program during execution is inconsistent with the access order specified by the program code, out-of-order memory access will occur.

Usually the program order is not equal to the memory order, resulting in out-of-order memory access

35. Please briefly describe the functions and usage scenarios of the FENCE.I instruction and the SFENCE.VMA instruction.

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The FENCE.I instruction is used as a synchronization primitive between cache instructions and prefetch instructions in the same CPU. In simple terms, it ensures that when the store instruction is visible to the CPU, the prefetch instruction is also visible to the CPU.

A simple implementation refreshes the local CPU's instruction cache and instruction pipeline. A more complex implementation can perform cache migration monitoring for each data instruction cache miss.

The SFENCE.VMA instruction constrains the order of memory accesses to ensure the correct execution of memory operations.

36. What is a process context switch? For RISC-V processors, what content needs to be saved during process context switching? Where is it saved?

——————

Switch from one process to the next process

The context that needs to be saved includes the values of S0-S11 registers, SP register, and ra register. Save them to task_struct->cup_context of the Netx process, and then restore the values of these registers in the processor from task_struct->cpu_context of the next process.

37. Assume that the scheduler switches process A to process B through the switch_to() function, then does process B immediately execute the callback function of thread B after the switch is completed?

_______

Some finishing work needs to be done for the kernel line layer A that has just been scheduled

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34. What is the cause of memory disorder? When
the actual memory access order of the program is inconsistent with the order specified by the program code during execution, memory disorder will occur.

35. Please briefly describe the role and usage scenarios of the FENCE.I instruction and the SFENCE.VMA instruction.
The role of FENCE.I is to ensure that the storage operation before the barrier has been completed and applied to the local CPU. The
role of SFENCE.VMA is to implement the synchronization operation of virtual memory management. The application scenarios are: 1) when the software changes the ASID of the process; 2) if the processor does not implement ASID or uses an ASID with a value of 0, when updating the satp register; 3) if the software modifies the page table entry outside the PTE; 4) if the software modifies the page table entry.
36. What is process context switching? For RISC-V processors, what content needs to be saved for process context switching? Where is it saved?
Process context switching refers to switching from the previous process to the next process through the switch function switch_to(), saving the context of the previous process during the switching process, and restoring the context of the next process.
The register contents that need to be saved are S0~S11, sp and ra, and saved to the cpu_context of the previous process.
37. Suppose the scheduler switches process A to process B through the switch_to() function. Then, does process B immediately execute the callback function of thread B after the switch is completed?
The callback function of thread B cannot be executed immediately, and some finishing work needs to be done for process A.

jobszheng5

34. Reply: In general, program order is not equal to memory order, resulting in memory disorder.
35. Reply: The FENCE.I instruction is used as a synchronization primitive between cache instructions and prefetch instructions in the same CPU. The goal is to ensure that when the store instruction is visible to the CPU, the prefetch instruction is also visible to the CPU. The SFENCE.VMA instruction constrains the memory access order of memory operations in order to ensure that memory operations are executed correctly.

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I have learned it, and this kind of learning is more effective!