Read "RISC-V Architecture Programming and Practice" Part 2 together and test the instructions with the hardware environment
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I have read the third and fourth chapters of this book in the past two days. Taking advantage of the enthusiasm of learning, I will review the previous hardware environment test and analysis.
After studying the contents of Chapter 3 and Chapter 4 of this book, let's build the hardware environment and test the RISC-V instructions.
Build a RISC-V development environment based on Eclipse + RISC-V gcc compiler in Windows environment, and cooperate with openocd debugging software to compile, download and debug RISC-V kernel programs.
The hardware chooses a RISC-V chip from GD
Create a project and select the model GD32VF103
I thought RISC-V only had so many instructions in the first article, but after reading it, I found out that Chapter 3 is the basic instruction set.
There are many other instruction sets, which we need to find in the RISC-V instruction set manual.
The 64-bit version of the RV32G instruction set is the RV64G instruction set. To switch to a 64-bit ISA, only a few instructions were added to the ISA. The instruction set only adds word, doubleword, and long versions of the 32-bit instructions, and extends all registers (including the PC) to 64 bits. So, sub in RV64I operates on two 64-bit numbers instead of 32-bit numbers in RV32I. RV64 is very close to RV32 but actually different; it adds a few instructions and the basic instructions do slightly different things than in RV32.
Here we mainly look at the multiplication and remainder instructions
Instructions can be found in the RISC-V manual.
I have done a review of GD before, but I didn't go into many assembly instructions. This time I can take a look at it.
square test
MULH[[S]U] rdh,rs1,rs2; MUL rdl,rs1,rs2
(The source register specifiers must be in the same order, and rdh cannot be rs1 or rs2.) So the microarchitecture can fuse these into a single multiply operation, rather than performing two separate multiplications.
The format of LW (load word) instruction is LW rd, offset(rs1). x[rd] = sext ( M [x[rs1] + sext(offset) ] [31:0] )
This instruction reads four bytes (one word) from the effective address and writes them into the rd register.
Let’s look at KEIL’s simulation
It looks like the assembly instructions are basically the same
Remainder Instructions
No instruction found in the remainder instruction CORTEX
The following figure shows RISC-V
Implemented by REMU instruction
SDIV Rd, Rn, Rm ;Rd = Rn/Rm
- Multiply and subtract MLS
MLS Rd, Rm, Rn, Ra ;Rd = Ra-Rm*Rn
CORTEX-M implements division and multiplication and subtraction instructions together.
The idea of implementing this remainder in CORTEX-M is roughly as follows: suppose there are two numbers, one is 15 and the other is 7, and to get the remainder, 15/7=2, the final implementation is 15-7*2=1
RSIC-V is implemented through a REMU, which is relatively fast
In general, RISC-V is highly scalable. RISC-V is a modular instruction set with the core being the RV32I instruction set. Other extension modules can be expanded by adding additional modules.
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