Allwinner T3 + FPGA domestic core board - FPGA program loading and solidification of Pango Design Suite

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Allwinner T3 + FPGA domestic core board - FPGA program loading and solidification of Pango Design Suite [Copy link]

This article mainly demonstrates the methods of loading, curing, and compiling FPGA programs based on the Pango Design Suite (PDS) software developed by Unigroup Tongchuang. The applicable development environment is Windows 7/10 64bit.

The test board is the Allwinner T3 + Logos FPGA core board, which is a heterogeneous multi-core domestic industrial core board based on the Allwinner Technology T3 quad-core ARM Cortex-A7 processor + Unisplendour Tongchuang Logos PGL25G/PGL50G FPGA design. The ARM Cortex-A7 processing unit has a main frequency of up to 1.2GHz. All components of the core board, including CPU, FPGA, ROM, RAM, power supply, crystal oscillator, connector, etc., are domestically produced industrial-grade solutions, with a localization rate of 100%.

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The T3 inside the core board is connected to Logos through SPI, CSI, and I2C communication buses, and the LVDS DISPLAY, RGB DISPLAY, MIPI DSI, TVOUT, TVIN, CSI, GMAC, EMAC, USB, SATA, SDIO, UART, SPI, TWI and other interfaces and FPGA IO pins are led out through industrial-grade B2B connectors, supporting dual-screen display, Mali400 MP2 GPU, and 1080P@45fps H.264 video hardware codec. The core board has been verified by professional PCB Layout and high and low temperature tests, and is stable and reliable, which can meet various industrial application environments.

The FPGA program is located in the Demo directory of the product information. Please copy the corresponding FPGA program to a non-Chinese path in Windows. The following table shows the directory structure of the FPGA program in the Demo directory and the main file description.

Table 1

Table of contents

Files/Directories

illustrate

bin

xxx.sbit

Executable program (BitStramFile file) for online loading

xxx.sfc

Executable program for flashing into SPI FLASH

project

xxx_pgl25g/xxx_pgl50g

constraints

Constraints File Directory

hdl

Verilog source code file directory

xxx.pds

Pango Design Suite Project File

Before following this document, please refer to the software installation documentation to install Pango Design Suite and connect the evaluation board to the PC through the FPGA downloader.

Program loading

This section takes the led_flash case as an example to demonstrate the program loading method.

1. Open the Windows Device Manager and check to confirm that the FPGA downloader is properly connected to the PC.

Figure 1

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Double-click "C:\pango\PDS_2021.1-SP7.1\bin\cdt_cfg.exe" in the Pango Design Suite installation directory to open the Fabric Configuration interface.

Figure 2

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Figure 3

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Power on the evaluation board, right-click on a blank area of the Fabric Configuration interface, and select "Scan Device" to scan and connect to the FPGA device through the FPGA downloader.

Figure 4

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After the connection is successful, the FPGA chip icon will appear and the FPGA program selection window will pop up automatically. Please select the corresponding xxx.sbit file to load.

Figure 5

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Figure 6

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Right-click the FPGA chip icon and select "Program..." to load the target program to the FPGA for execution.

Figure 7

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Figure 8

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After the program is successfully loaded, the Console will print and display the message "COMMAND [Program] execute successfully". At the same time, you can observe that the evaluation board LED turns on and off at a certain time interval, indicating that the program is loaded and running normally online.

Figure 9

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Program solidification

This section takes the led_flash case as an example to demonstrate the program solidification method.

Double-click "C:\pango\PDS_2021.1-SP7.1\bin\cdt_cfg.exe" in the Pango Design Suite installation directory to open the Fabric Configuration interface.

Fig.10

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Power on the evaluation board, right-click on a blank area of the Fabric Configuration interface, and select "Scan Device" to scan and connect to the FPGA device through the FPGA downloader.

Fig.11

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After the connection is successful, the FPGA chip icon will appear and the FPGA program selection window will pop up automatically. Click Cancel to not load the xxx.sbit file.

Fig.12

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Right-click the FPGA chip icon and select "Scan Outer Flash" to scan and identify the SPI FLASH chip.

Fig.13

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After the scan is successful, a file selection window will pop up automatically, select the xxx.sfc file to be solidified.

Fig.14

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Right-click the "Outer Flash" chip icon and select "Program..." to solidify the program.

Fig.15

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After the program is solidified, the Console will print and display the following information.

Fig.17

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Disconnect the evaluation board from the FPGA downloader and power it on again. You can observe that the LED on the evaluation board turns on and off in a cycle at a certain time interval, indicating that the program has been successfully solidified and is running normally.

Project import and program compilation

If you need to import a project and recompile the program, please follow the steps below. If you do not need to import a project or recompile the program, please ignore this section.

This section uses the led_flash case as an example to demonstrate the steps of importing and compiling FPGA projects based on Pango Design Suite.

Project Import

1. Please double-click the Pango Design Suite icon on the desktop to open the software.

Fig.18

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Click "Open Project" in the pop-up interface.

Fig.19

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In the pop-up interface, select the xxx.pds file in the FPGA case "project\led_flash_xxx\ directory and click Open to open it.

Fig. 20

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The following interface pops up and the project import is completed.

Fig.21

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New construction and transplantation

This section mainly describes the steps to create a new project and migrate an existing project. If you do not need to create a new project or migrate an existing project, please skip this section.

1. Double-click to open Pango Design Suite and click "New Project" in the pop-up interface.

Fig. 22

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1. In the pop-up interface, click Next to jump to the next interface.

Fig.23

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1. Enter the project name, modify the file save path according to the actual situation, and click Next.

Fig.24

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1. In the pop-up interface, check "RTL project" and click Next.

Fig.25

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1. The Add Design Source Files interface below pops up. Just click Next to skip it.

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1. The following Add Existing IP interface pops up. Just click Next to skip it.

Fig. 27

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The following Add Constraints interface pops up. Just click Next to skip it.

Fig.28

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In the pop-up project configuration interface, set the FPGA chip parameters. Family: Logos, Device: PGL25G, Package: MBG324, Speed: -6, Synthesis Tool: ADS. After the settings are completed, please click Next.

Fig.29

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In the pop-up interface, click Finish to complete the project creation.

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Fig.31

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In the project interface, right-click the project Designs and click "Add Source" to create a new module file.

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In the following pop-up interface, select "Add or create design sources" and click Next.

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In the pop-up interface, click the "Create File" option, enter the name of the new module file, and click OK in sequence.

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In the pop-up interface, you can directly configure pin constraints through the graphical interface. Since this demonstration uses a new constraint file to configure pin constraints, please click OK to skip.

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After completing the creation of the module file, the program editing window will appear on the right side of the project interface.

Fig.37

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Open the case "project\led_flash_xxx\hdl\led_test.v" file, copy all the codes to the program editing interface or write them yourself, and click Save to edit. After saving, if there are no Errors and Warnings in the Console window, it means that there are no errors in the program syntax.

Fig.38

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In the project interface, right-click "Constraints -> Add Source" to make pin constraints.

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In the pop-up interface, select "Add or create constraint sources" and click Next.

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In the pop-up interface, click the "Create File" option, enter the name of the new pin constraint file, and click OK in sequence.

Fig.42

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After the pin constraint file is created, double-click to open the xxx.fdc file in the project interface, as shown in the figure below.

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In the following interface option bar, click "Device -> IO" in sequence, and generate a pin constraint list in the "Tool Tabs" window according to the project xxx.v file. Please select the pin according to the hardware connection.

Fig.46

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After the pin selection is completed, the interface is shown as below. At this point, the FPGA project is created.

Fig.47

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Program Compilation

1. Double-click "Generate Bitstream" to compile the FPGA program.

Fig.48

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After programming is completed, the Console window will print the message: Process "Generate Bitstream" done, and generate the xxx.sbit file in the generate_bitstream directory of the FPGA project.

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Fig.50

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To generate the xxx.sfc file for flashing to SPI FLASH, please follow the steps below.

1. Click "Tools -> Configuration" in the menu bar to enter the Fabric Configuration interface, and click "Operations -> Convert File" in the menu bar.

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In the pop-up interface, please configure the SPI FLASH information according to the method shown below. Factory Name: WINBOND, Device Name: W25Q64Q (SPI FLASH chip model), BitStramFile: BitStramFile file (xxx.sbit) path, Output File Name: Generate xxx.sfc file save path (by default, saved in the same directory as the BitStramFile file). After the configuration is completed, please click OK to save the configuration.

Fig.53

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The following interface pops up, please click OK. The xxx.sfc file for flashing to SPI FLASH has been successfully generated.

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