Domestic FPGA Anlu high integration low power consumption SF1 series FPSoC new product evaluation [using SF1 uart IP core communication]

Grayson__

Domestic FPGA Anlu high integration low power consumption SF1 series FPSoC new product evaluation [using SF1 uart IP core communication] [Copy link]

 

In the last issue, we used the UART communication in the MCU. In this issue, we use the UART IP core of SF1 to conduct a communication experiment between the computer and the FPGA.

First, create a new TD project, select uart in ip generator, change the input clock frequency to 25MHz, baud rate to 115200, data bit to 8 bits, stop bit to 1 bit, as shown in the figure below

The top-level code is as follows. Its function is to send 8'hf0 to the computer serial port when the data received by the FPGA is 8'h32:

module uart_top( 
	input			clk,
    input			rst_n,
    input			rxd,
    output			txd 
);

wire	[7:0]	tx_data;
wire	[7:0]	rx_data;
wire		rx_vld;	
wire		tx_en;
uart_interface uart_interface_u1(
  .clk(clk),
  .rst_n(rst_n),
  .rxd(rxd),
  .tx_data(tx_data),
  .tx_en(tx_en),
  .rx_data(rx_data),
  .rx_err(),
  .rx_vld(),
  .tx_rdy(),
  .txd(txd)
);
assign tx_data = 8'hf0;
assign tx_en = rx_data==8'h32 ? 1'b1 : 1'b0;

endmodule

The results are as follows:

However, a problem was encountered during the experiment. No matter whether the highest bit of the 8-bit data sent by the FPGA was 0 or 1, the highest bit of the 8-bit data received by the computer was always 1. For example, when 8'h01 was sent, the computer displayed the received data as 81 (hexadecimal).

Hope to get on-demand support from peers.

fxyc87

Check with an oscilloscope. The official IP core shouldn't be that bad, right? Also, the error is too large, exceeding 3%.

Jacktang

What are the main precautions for using SF1's uart ip core to conduct a communication experiment between a computer and FPGA?

Grayson__

Jacktang posted on 2023-3-12 09:22 What are the main precautions for using SF1's uart ip core to conduct a communication experiment between a computer and FPGA?

Incoming clock rate: The frequency range is <= 200Mhz, and the default is 50 000 000Hz. The specific restrictions for different baud rates are as follows:

When the baud rate is 9600, the input clock requirement is >= 2MHz;

When the baud rate is 19200, the input clock requirement is >= 4MHz;

When the baud rate is 38400, the input clock requirement is >= 8MHz;

When the baud rate is 57600, the input clock requirement is >= 12MHz;

When the baud rate is 115200, the input clock must be >= 24MHz.

Grayson__

fxyc87 posted on 2023-3-12 09:22 Using an oscilloscope, the official IP core should not be so bad, right? Also, the error is too large, exceeding 3%.

In the IP core, re-set the baud rate to a smaller value, such as 57600, 38400, etc., and the data sent by the FPGA received by the computer will be correct.

Jacktang

Grayson__ posted on 2023-3-12 11:24 Incoming clock rate Input frequency: The frequency range is <= 200Mhz, the default is 50 000 000Hz. For different baud rates...

OK, thanks