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What does this sentence mean? How to understand it? [Copy link]

I saw a Verilog program to drive LCD1602, the code is as follows:

module LCD1602(                //50Mhz
         clk,rst_n,            //input
          
         lcd_en,lcd_rw,lcd_rs,  
         lcd_data
);
 
input clk,rst_n;
output lcd_rw;
output reg lcd_rs;
output wire lcd_en;
output reg [7:0] lcd_data;
//-------------------------------------

assign lcd_rw=1'b0;     //设置高延迟 就不check busy 无需读取状态
//--------------input clk 50000,000----------------------
//---------------2^16==65536>50000 1ms-------------------
//------------------------分频成1ms---------------------
reg [15:0] cnt;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n) cnt<=16'b0;
    else if(cnt==50_000) cnt<=16'b0;
    else cnt=cnt+1'b1;
end
 
reg [3:0] ms;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n) ms<=1'b0;
    else if(cnt==50_000) ms<=ms+1'b1;
end
 
//--------------------------------------------------------
//初始化以及显示字符  只初始化一次 一直显示一个字符
parameter lcd1=4'b0000;
parameter lcd2=4'b0001;
parameter lcd3=4'b0010;
parameter lcd4=4'b0011;
parameter lcd5=4'b0100;
parameter lcd6=4'b0101;
parameter lcd7=4'b0110;
parameter lcd8=4'b0111;
parameter lcd9=4'b1000; 
//状态转移
reg [2:0] current_state,next_state;
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n) current_state<=0;
    //一开始设置的条件是  ms==15 但是时钟是clk 所以状态会一直转移 无法正确驱动lcd
    // add cnt==16'h0000   确保状态只转移一次
    else if(ms==15 && cnt==16'h0000)  
         current_state<=next_state; 
end
 
//判断下一个状态 初始化完了之后一直循环1个状态
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n) next_state<=lcd1;
    else
     case(current_state)
      lcd1:next_state<=lcd2;
      lcd2:next_state<=lcd3;
      lcd3:next_state<=lcd4;
      lcd4:next_state<=lcd5;
      lcd5:next_state<=lcd6;
      lcd6:next_state<=lcd7;
      lcd7:next_state<=lcd8;
      lcd8:next_state<=lcd8;
		//lcd9:next_state<=lcd9;
     endcase
end
 
//根据状态输出相应数据
always@(posedge clk or negedge rst_n)
begin
    if(!rst_n) 
    begin
        lcd_rs=0;
    end
    else
     case(current_state)
      lcd1:begin lcd_rs=0; lcd_data=8'h38; end
      lcd2:begin lcd_rs=0; lcd_data=8'h08;  end
      lcd3:begin lcd_rs=0; lcd_data=8'h01;  end
      lcd4:begin lcd_rs=0; lcd_data=8'h06;  end
      lcd5:begin lcd_rs=0; lcd_data=8'h0c;  end
      lcd6:begin lcd_rs=1; lcd_data="h";  end       //cs
      lcd7:begin lcd_rs=1; lcd_data="a";  end       //show
      lcd8:begin lcd_rs=1; lcd_data="h";  end       //cs
		//lcd9:;       //cs    
		//default:;
     endcase
end
 
//----------------lcd_en使能1ms---------------------
assign lcd_en=current_state==lcd8?1'b0:ms==15?1'b1:1'b0;
//assign lcd_en=current_state==lcd8?1'b0:ms==15?(cnt[15]==1?1'b1:1'b0):1'b0;  //以上会多输出一个a
endmodule 

After the program is downloaded, it should display "hah", but it displays "haa"

And this one:

assign lcd_en=current_state==lcd8?1'b0:ms==15?1'b1:1'b0;

How should I understand this sentence? I am confused by it. Thank you!

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assign lcd_en=current_state==lcd8?1'b0:ms==15?1'b1:1'b0; if (current_state==lcd8) lcd_en=1'b0 else if(ms==15) lcd_en=1'b1 else lcd_en=1'b0   Details Published on 2022-10-17 00:31
Personal signature为江山踏坏了乌骓马,为社稷拉断了宝雕弓。
 

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This "?" should represent a judgment. If it is true, the following statement will be executed. If it is not true, the statement after ":" will be executed. Your code is equivalent to having two nested judgment statements.
This post is from EE_FPGA Learning Park
 
 

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assign lcd_en=current_state==lcd8?1'b0:ms==15?1'b1:1'b0;

if (current_state==lcd8) lcd_en=1'b0

else

if(ms==15) lcd_en=1'b1

else

lcd_en=1'b0

This post is from EE_FPGA Learning Park
 
 
 

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Thank you both

This post is from EE_FPGA Learning Park
Personal signature为江山踏坏了乌骓马,为社稷拉断了宝雕弓。
 
 
 

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