Anlu SparkRoad Development Board Review (9) Use of on-chip SDRAM, TD debugging function

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Anlu SparkRoad Development Board Review (9) Use of on-chip SDRAM, TD debugging function [Copy link]

 

　　The FPGA of Anlu EG4S20 has built-in SDRAM. If necessary, you can directly use the on-chip SDRAM to avoid external SDRAM occupying many pin resources and save the work of SDRAM layout and wiring. In the selection dialog box of IP generator, you can see the IP of SDRAM.

　　I felt that it would be much more convenient to use with an IP, but when I clicked in, I was a little disappointed...

　　It is just an SDRAM, and its pins are the same as an SDRAM connected to the chip. The IP does not have a controller, so it only saves the allocation of FPGA pins, and its usage is the same as that of an external SDRAM.

　　Since I have never written the logic for operating SDRAM, I will use SDRAM_TEST in Anlu Demo to take a look.

　　When referencing the on-chip SDRAM, using IP means that the SDRAM signal is not drawn out from the top layer. The on-chip SDRAM data bit width is 32. This demo contains a simple SDRAM controller. The external state machine is used to operate the controller to perform some tests, and the numbers displayed on the digital tube are constantly changing.

　　However, the controller interface is not commented and it is not easy to know how to use it at a glance. It takes some effort to connect it with the RISC-V CPU IP (it can only be connected through the RISC-V external bus, but that bus does not support wait states, so it is not suitable to directly read SDRAM). So forget it.

　　Then use the debugging function of TD software to check the SDRAM signal.

　　TD comes with two debugging tools: Chip probe and Chip watcher.

　　What is the function of chip probe? Click to see

　　It means that the internal signal can be brought to an FPGA pin without re-synthesis. If I don’t have this tool, when I need to bring out the signal of an internal module when debugging FPGA (for example, connecting an oscilloscope for logic analysis), I need to modify the code layer by layer to add an output port, then assign an IO port, and re-synthesize.

　　Try to look at the SD_WE_N signal, but you can’t find it?

　　Give up, just watch two that are watchable, choose from all the listed ones.

　　After clicking "Check and save all changes", TD will run the process. Although the code is not re-synthesized, the layout and routing may still be redone, and the Bit stream is regenerated and needs to be downloaded again.

　　Connect the oscilloscope to the B15 and C11 pins, and you can see the signal specified by the chip probe. Because the switching speed is too fast, it seems that the clip probe cannot keep up.

　　Chip Watcher is another tool that comes with TD. It can be connected via JTAG and the signals can be observed in the software.

　　First add the signal, the same dialog box as the chip probe appears, and there is the same problem, not all signals are available. I randomly selected a few and added them.

　　You also need to select a clock and a sampling depth.

　　Then the TD prompts you to run the process again, and the logic required by the chip watcher will be automatically added. After generating a new bit file, you need to download it again before you can use the chip watcher to view the signal.

　　After downloading, you can directly switch to the Data page to view it. There are two capture methods: single trigger and continuous trigger.

　　However, there is no time scale zoom control? It is not convenient to see clearly, and it is difficult to deal with more complex problems. There is also the problem of sampling speed, after all, the transmission speed of JTAG is too slow.

　　In short, the chip probe and chip watcher functions of TD software provide a little convenience for debugging, but they are not powerful. It is better than nothing, and it is helpful if you happen to need it.

　　Apart from the function itself, the interface design of TD software has many imperfections, which will affect the operation efficiency. Some forum friends have complained a lot, so I won't say more.

littleshrimp

I didn't find any problems with Anlu's hardware, and I think the design of the development board is pretty good. The software is very lame, the IDE seems to be developed by amateurs, the manual is written casually, the official IPs are relatively few, and some IPs also look casual. The overall idea is to write whatever comes to mind, without a unified standard reference. I don't know what the demo has to do with Verimake, it seems that the software is outsourced.