Anlu SparkRoad Development Board Review (2) Simple Operation of Integrated Development Environment

cruelfox

Anlu SparkRoad Development Board Review (2) Simple Operation of Integrated Development Environment [Copy link]

 

　　The FPGA integrated development environment provided by Anlu has a grand name: Tang Dynasty, or TD for short. Its functions are similar to those of Altera's Quartus II and Xilinx's ISE.

　　After installing TD, it takes up more than 800 MB, which is less than the Qualtus 9.1 web version I have been using. When I start the software, my first impression is that the interface is really simple and friendly to beginners. However, it can only run on Windows 7.

　　Let's create a simple project. Look at the File menu bar, there is no New Project item. Oh, just go to the Project menu bar, select New Project, and a dialog box will appear.

　　This step is to fill in the name, select the project path (TD will create a subdirectory with the project name under the path), select the specific FPGA model to be used, and then confirm. There are no extra steps.

　　Next, let's write a simple logic using switches and LEDs. Create a new Verilog source file, name it test.v, and add it to the project.

　　TD's editor has an automatic completion function, but I am not used to it and I can't find where to turn it off. Fortunately, TD provides the option to call an external editor. After saving the source file, TD will perform syntax checking and other tasks, which can detect writing errors in advance. This function is practical (the Quartus I use does not have it, and it will only be checked during the synthesis stage, which affects efficiency).

　　TD automatically recognizes the test module you wrote and sets it as the top-level module of the project, so you don't have to set it manually. Then, click the green round button on the toolbar to start the synthesis work.

　　At this time, the console subwindow below will output a lot of information. If an error occurs and the system stops, you can see the reason here.

　　If everything is normal, you will see TD prompt that the .bit file has been generated and can be downloaded to the FPGA.

　　However, there is still one thing missing: assign input and output pins to the written logic and associate them with the chip. I used a clock input pin, 16 switch inputs, and 16 LED outputs. You need to find where to assign pins. Look at the menu bar. There is an I/O Constraint column under Tools. That should be it.

　　The dialog box is called up. The lower part is a table that lists the used I/O. Since there is no allocation, the Bank and Location columns are empty. You only need to fill in the FPGA pin name in each row of the Location column, and the Bank will be automatically displayed. This step should be performed according to the circuit diagram of the SparkRoad board. If you fill in the wrong information, you will not achieve the desired effect.

　　After filling in, you will be prompted to save it as a constraint file with the suffix .adc. You can see it in the tree diagram on the left side of the project, and you can open the file for editing.

　　You can see that this constraint file is in text format, and the pin assignment is clear at a glance. Since it is in text format, you can just copy and edit it when reusing it between projects, without having to enter it according to the diagram.

　　You can click on the Design Summary in the lower left corner to view the report. The RTL summary is the result of logic synthesis, summarizing how many D flip-flops and basic logic are used. The Gate summary is the resources occupied by implementing this logic in the FPGA. There is also a Physical summary that contains a report on each pin used.

　　Because this simple project does not use clock constraints, there is no Timing summary, etc.

　　Finally, download the generated bit stream to the FPGA. After connecting the board, click the download button on the far right of the toolbar, a dialog box will appear, select the generated .bit file, and then click "Run" to start downloading. The green progress bar below will start moving.

　　After the download is complete, you can see the LED on the board start blinking.

demo.mp4 (95.45 KB, downloads: 3)

2022-4-12 22:10 上传

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　　Because this FPGA does not contain flash, you can use JTAG to configure the logic into it during the development stage; but when it is used as a product, the FPGA must read the configuration from the external flash device. For example, to solidify the logic written above on the board, you still need to burn the flash. Fortunately, TD software is very simple to do this step. Just change the Mode from the default "JTAG" to "PROGRAM FLASH" when downloading.

　　Summary: TD software (Tang Dynasty) has a simple interface, is easy to use and friendly to beginners.

Jacktang

When downloading, change the Mode from the default "JTAG" to "PROGRAM FLASH", it works, thanks for sharing

littleshrimp

I just read your post and it's comfortable. What I'm more surprised about is "Tang Dynasty", why there is no Chinese support?

cruelfox

littleshrimp posted on 2022-4-13 18:55 I feel comfortable with your post. What I find strange is that "Tang Dynasty" has no Chinese support.

Chinese support? I didn't try to write Chinese in the code. You mean the Chinese interface?

Let me guess. To make a Chinese interface, software development investment is required (and it needs people who are good at Chinese). Maybe the company thinks it is unnecessary, and the English interface is popular with users all over the world. We have popularized English teaching in elementary schools. Those who can learn FPGA should have enough English. The problem of not being able to understand the terminology is not the fault of English, because it is a word invented by foreigners, and those who don’t understand it when translated into Chinese still don’t understand it. I don’t know whether the Chinese terms for the relevant terminology are unified. If the translation is not appropriate, it will be difficult to understand.

littleshrimp

cruelfox posted on 2022-4-13 20:37 Chinese support? I didn't try to write Chinese in the code. You mean the Chinese interface. Let me guess, making a Chinese interface requires software development...

It shouldn't be that difficult to make a Chinese page. You can just write a language pack, such as an XML file, to solve the problem (unless the multi-language problem was not considered during the initial design). I don't know much about translation, but it doesn't seem that difficult. After all, domestic high-tech companies can write English interfaces.

cruelfox

littleshrimp posted on 2022-4-13 21:16 It shouldn't be so troublesome to make a Chinese page. In terms of software, writing a language pack, such as an XML file, can solve the problem (unless it was not designed in the first place...

Language pack, is this your idea for making a web page?

When programming software, it is easier to make an English interface. Different languages may not have the same words for the same meaning, and the length of the displayed string is different. These details require a lot of effort. I think the Chinese version of Windows is too awkward in some places.

FPGA software is something that was already available from others, so I learned it from them. The terminology was already available from others, so it’s not that writing an English interface is difficult.

littleshrimp

cruelfox posted on 2022-4-14 11:58 Language pack, this is your idea of making a web page. When you write software, almost all of them are in English. Different languages may not have the same meaning...

You don't have to doubt the language pack. Both Android and CSharp support this method. It is a common technology in interface development today. For example, for a "Submit" button, you can write the "Submit" string into the control, or you can associate it with a certain ID in the resource file and index the corresponding string. This makes it more convenient for multiple languages and later modifications.

The typesetting problem you mentioned does exist, but it doesn't seem to be a technical problem that cannot be solved. I can only say that FPGA is considered to be a relatively high-threshold thing by many people, and manufacturers assume that people who study FPGA should have a good foundation in English.