[Fudan Micro FM33LG0 Series Development Board Review] OPA Function Analysis

北方

[Fudan Micro FM33LG0 Series Development Board Review] OPA Function Analysis [Copy link]

 

1. Chip Function

The main features of FM33LG0 include wide voltage range of 1.65~5.5V, maximum main frequency of 64Mhz, 64/128/256KB Flash, 16/32/32KB RAM, 12bit 2Msps SAR-ADC and 12bit 1Msps DAC, maximum support of 4COM×44SEG/6COM×42SEG/8COM×40SEG, ES supports ECB/CBC/CTR/GCM/GMAC modes, and the functional logic block diagram is as follows.

It can be powered by batteries at low power consumption, and the power supply circuit is relatively simple. The maximum port voltage can reach 6.5V, which is quite impressive and can be compared with Renesas. The operating current is about 6.16mA under standard operation, and the low power consumption is calculated in uA.

When the chip is booted from Flash, the address space allocation of FM33LG048 is as shown below (256KB Flash, 32KB RAM) Storage space allocation

The chip's PMU management and reference voltage all provide high-precision and high-level chip technology. The CPU core is Cortex-M0+, which complies with the ARMv6-M architecture and programming model.

2. OPA Function Introduction

When the power amplifier function is used, the CMRR common mode rejection ratio is 66~70dB. FM33LG0 integrates an operational amplifier, which can be used to amplify weak input signals or for impedance matching of weak drive signals.

Typical GBW 2MHz; Typical power consumption 150uA (normal mode), 2uA (low power mode); Maximum drive current 500uA; Supports standalone mode, buffer mode, PGA mode (x2, x4, x8, x16); OPA output can be connected to ADC.

The OPA input has 4 channels, and the OPA output is connected to 4 GPIOs, of which OPA1_OUT1 does not pass through the analog switch to optimize the output impedance; the other 3 output paths pass through the analog switch and are closed by default.

By selecting different AMUX paths according to register configuration, different closed-loop applications can be realized, such as buffer, PGA (built-in feedback resistor), independent op amp. The output can be drawn from IO, or connected to ADC, or generate digital signals or interrupt output.

In standalone mode, the output is configured through the external Rf to configure the op amp multiples.

In buffer mode, the OPA can be used to provide impedance adjustment for the ADC input. When the input signal frequency is compatible with the GBW of the OPA, the OPA configured in buffer mode can enhance the driving capability of the ADC input signal.

Software configuration method: Configure OPAxCR.VPSEL and VNSEL to select input IO; Configure OPAxCR.OPAxMOD to 11, that is, buffer mode; Enable OPAx.

In PGA mode, a DC bias can be applied to the positive end of the OPA through the DAC, which can come from the DAC or from an external voltage source.

3. Example code analysis

The example code uses PGA mode as follows. The main program is main.C

int main(void)
{
    MF_Clock_Init();
    MF_SystemClock_Config();
    FL_Init();
    MF_Config_Init();
    UserInit();
    Test_OPA1PGA();
    while(1)
    {
        //        LED0_TOG();
        //        FL_DelayMs(1000);
    }
}

The specific function has been encapsulated. First configure it, then enable it to start the function.

void Test_OPA1PGA(void)
{
    //OPA_PGA_NOINVERT_Init();
    OPA_PGA_INVERT_Init();
    FL_OPA_Enable(OPA);
}

The initialization process is to select the GPIO direction, and then set the OPA function and configuration. The code is as follows

void OPA_PGA_INVERT_Init(void)
{
    FL_GPIO_InitTypeDef    GPIO_InitStruct;
    FL_OPA_InitTypeDef     OPA1_InitStruct;
    //OPA1正端输入，INP1
    GPIO_InitStruct.pin         = FL_GPIO_PIN_11;
    GPIO_InitStruct.mode        = FL_GPIO_MODE_ANALOG;
    GPIO_InitStruct.outputType  = FL_GPIO_OUTPUT_PUSHPULL;
    GPIO_InitStruct.pull        = FL_DISABLE;
    GPIO_InitStruct.remapPin    = FL_DISABLE;
    FL_GPIO_Init(GPIOB, &GPIO_InitStruct);
    //OPA1负端输入，INN2
    GPIO_InitStruct.pin         = FL_GPIO_PIN_6;
    GPIO_InitStruct.mode        = FL_GPIO_MODE_ANALOG;
    GPIO_InitStruct.outputType  = FL_GPIO_OUTPUT_PUSHPULL;
    GPIO_InitStruct.pull        = FL_DISABLE;
    GPIO_InitStruct.remapPin    = FL_DISABLE;
    FL_GPIO_Init(GPIOA, &GPIO_InitStruct);
    //OPA1输出，OUT
    GPIO_InitStruct.pin         = FL_GPIO_PIN_12;
    GPIO_InitStruct.mode        = FL_GPIO_MODE_ANALOG;
    GPIO_InitStruct.outputType  = FL_GPIO_OUTPUT_PUSHPULL;
    GPIO_InitStruct.pull        = FL_DISABLE;
    GPIO_InitStruct.remapPin    = FL_DISABLE;
    FL_GPIO_Init(GPIOB, &GPIO_InitStruct);
    //OPA1配置
    OPA1_InitStruct.INP              = FL_OPA_INP_SOURCE_INP1;
    OPA1_InitStruct.INN              = FL_OPA_INN_SOURCE_INN2;   //只有INN2通道支持反相PGA模式
    OPA1_InitStruct.mode             = FL_OPA_MODE_PGA;
    OPA1_InitStruct.negtiveToPin     = FL_DISABLE;
    OPA1_InitStruct.gain             = FL_OPA_GAIN_INVERT_X7;
    OPA1_InitStruct.lowPowermode     = FL_DISABLE;
    OPA1_InitStruct.PGAModeSelect    = FL_OPA_PGA_MODE_FB_TO_NEGATIVE;
    FL_OPA_Init(OPA, &OPA1_InitStruct);

}

The mode selection is set to FL_OPA_MODE_PGA;

4. Testing and verification

Start the project directly.

After compiling and downloading to the development board, you can display the input and output functions.

Jacktang

The operating current of FM33LG0 under standard operation is 6.16mA. Low power consumption is calculated in uA. It is OK in terms of low power consumption.

北方

Jacktang published on 2021-12-1 07:31 The operating current of FM33LG0 under standard operation is 6.16mA, and the low power consumption is calculated in uA. It is okay in terms of low power consumption

This model is mainly low power consumption, and it is still very good under the nominal value. The working current is normal, and low power consumption means the control of leakage current.

TI is quite exaggerated, claiming that it can reach the nA level. However, during the implementation process, it is necessary to control the power consumption of the application through programming technology.