[Fudan Micro FM33LG0 Series Development Board Review] PGL Function and Brief Analysis

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[Fudan Micro FM33LG0 Series Development Board Review] PGL Function and Brief Analysis [Copy link]

 

1. PGL function

Compared with other series, the unique feature of Fudan Micro FM33LG0 is PGL, which is not available in FM33LC series. The specific explanation in the manual is as follows

Programmable Glue Logic is a simple programmable logic based on a lookup table (LUT). Its input and output can be connected to chip pins and internal signals to implement some simple glue logic. In some applications, it can help system design reduce the number of logic devices on the PCB. Each LUT contains 4 inputs, 1 output, 1 truth table, and optional synchronization/filtering circuits. Users can obtain the desired combinational logic output expression by programming the truth table. Each input signal can be individually shielded.

The basic features of PGL are as follows:

Implement simple glue logic to simplify PCB design

4 4-input lookup tables

Logical expressions such as AND, NAND, OR, NOR, XOR, NOT, etc. can be implemented through truth table programming

Timing synchronization or filtering

Flexible LUT input selection: IO, internal signal, other LUT output

Output can be connected to IO or other peripheral triggers

The specific logic diagram is as follows:

In fact, it is a logic chip that can be implemented by table lookup method, and in NXP it is implemented as a PLC function.

A total of 4 units above are included.

However, the pins of this PGL cannot be customized, but have been assigned to fixed pins.

2. PGL programming instructions

During programming, when using LUT pin input, you need to configure the corresponding pin as GPIO input, clear the input MASK register, and enable LUT. When using LUT pin output, you need to configure the corresponding pin as a digital function, configure the pin as a LUT output through the digital function selection register, and then enable LUT. This function is usually implemented in the initialization function of GPL_init(), as shown in the following sample code

void PGL_Init()
{
    FL_GPIO_InitTypeDef    GPIO_InitStruct = {0};
    FL_PGL_LUT_InitTypeDef lutInit;

    /*PC2、PC3为LUT0输入端口，配置成输入模式*/
    GPIO_InitStruct.pin = FL_GPIO_PIN_2 | FL_GPIO_PIN_3;
    GPIO_InitStruct.mode = FL_GPIO_MODE_INPUT;
    GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
    GPIO_InitStruct.pull = FL_DISABLE;
    GPIO_InitStruct.remapPin = FL_DISABLE;
    FL_GPIO_Init(GPIOC, &GPIO_InitStruct);

    /*PC0为LUT0输出端口，配置成数字模式*/
    GPIO_InitStruct.pin = FL_GPIO_PIN_0;
    GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
    GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
    GPIO_InitStruct.pull = FL_DISABLE;
    GPIO_InitStruct.remapPin = FL_ENABLE;//数字功能复用
    FL_GPIO_Init(GPIOC, &GPIO_InitStruct);

    /*PGL结构体配置*/
    lutInit.edge                = FL_PGL_LUT_EDGE_NONE;
    lutInit.outMode             = FL_PGL_LUT_OUTPUT_COMBINE_LOGIC;
    lutInit.input3              = FL_PGL_LUT_INPUT_DISABLE;
    lutInit.input2              = FL_PGL_LUT_INPUT_DISABLE;
    lutInit.input1              = FL_PGL_LUT_INPUT_GROUP0;
    lutInit.input0              = FL_PGL_LUT_INPUT_GROUP0;
    FL_PGL_LUT_Init(PGL, FL_PGL_LUT0, &lutInit);

}

This code is the process of initializing the first unit LUT0.

The truth table is written and read during use. By querying the data in the LUT truth table through the input state combination, the desired combinational logic function can be obtained. Each LUT supports 4 inputs, and the input can be used as an address to query 16 outputs. The LUT itself is a 4-bit addressable storage space. Register TRUTH[15:0] stores 16 output data, and the address correspondence is shown in the following table.

In the input section is the LUT input:

Each LUT has 4 inputs, each of which can come from a pin, a chip peripheral, or another LUT output. The LUT input signal source can be selected through the INSEL register.

LUT Output:

The output of the LUT can be connected to a pin, or to another LUT input.

This configuration still has a certain degree of flexibility. The four groups of LUTs can be cascaded or connected in parallel to achieve more complex logic or expand the number of bits of logic input.

3. Sample Code

In the code provided by the official website, there is a PGL routine that implements the above process very concisely.

Start the clock and hardware in the main program, and then initialize PGL according to the above method.

int main(void)
{
    /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
    /* SHOULD BE KEPT!!! */
    MF_Clock_Init();

    /* Configure the system clock */
    /* SHOULD BE KEPT!!! */
    MF_SystemClock_Config();

    /* Initialize FL Driver Library */
    /* SHOULD BE KEPT!!! */
    FL_Init();

    /* Initialize all configured peripherals */
    /* SHOULD BE KEPT!!! */
    MF_Config_Init();

    UserInit();
    Test_PGL();

    while(1)
    {
        LED0_TOG();
        FL_DelayMs(1000);
    }
}

The test is very simple to implement. Simply set the truth table to start the PGL function.

void Test_PGL()
{
    PGL_Init();
    /*真值表配置*/
    FL_PGL_WriteLUTTruthTable(PGL, FL_PGL_LUT0, 0x7);
    /*LUT使能*/
    FL_PGL_EnableLUT(PGL, FL_PGL_LUT0);
}

When PGL is started, the output is accessed according to the truth table. The above truth table is set to 0x7, which is converted into binary as 0111. Because only PC2 and PC3 are accessed as the inputs of LUT0-0 and LUT0-1, the actual output is formed.

The specific implementation method can be found in the following example.

After compiling in KEIL, you can download it to the development board for execution.

By changing the truth table, you change the logic setup.

In comparison, some internal logic functions can still be implemented, saving a logic element.