I used a better board, but I didn’t expect DDR4 to be…???

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I used a better board, but I didn’t expect DDR4 to be…??? [Copy link]

Author: Sun Yiwen, member of Yibo Technology Expressway self-media

Today's wind is very noisy, and there are a lot of cars on Shennan Avenue. In a building in the Science and Technology Park, after solving the impedance test problem last time, the siege lion Leibao has done another interesting project. The background is as follows:

DDR4 simulation of a CPU chip. The design adopts a single-sided fly-by, one-to-nine chip design. The operating data rate is 3200Mbps.

The hand-drawn structure is as follows:

Its structure is ordinary, so it must be a regular case.

Leibao follows the steps, sets up the stacking, builds the model, and edits the pattern - RUN. First, extract an address signal and directly observe the eye diagram and waveform of the DDR chip U1 with the worst signal quality:

Although the eye diagram and waveform of U1 seem to have large jitter and small margin, they are still a certain distance away from the level of the judgment standard. In short, the result is PASS.

As a simulation engineer, we always strive for excellence. How can we continue to optimize the signal quality? Lei Bao carefully checked the PCB and considered some conventional operations. There was not much room for optimization. Would it be better to change to a high-speed board?

Duang, it was quickly changed to M6g board, and then the stacking parameters were set, the impedance was controlled to be the same as before, and the signal topology remained unchanged, and the second round of simulation began.

Continue to observe the eye diagram and waveform of U1.

As a result, the worst point actually hits the level of the judgment standard? ? ? Don't come over here!

The signal quality of the FR4 board with normal loss meets the requirements, but the low-loss M6g board has problems.

Lei Bao scratched his head and fell into deep thought...

Combining the theoretical knowledge learned, Lei Bao analyzed the two simulation environments and got some clues.

The reasons are roughly analyzed as follows:

First, the chip driving ability is too strong.

After carefully looking at the IBIS model of the CPU, the driving rise time is very short and the rising edge is very steep. Using the IBIS software to view the Rising Waveform of the address line calling buffer, you can see the following figure:

Selecting 20%-80% of the highest level, the rise time in Middle mode is only about 56ps. According to past experience, the rise time of DDR4 signals is mostly between 100ps-200ps, and there are relatively few around the value of 56ps. In comparison, the rising edge of the signal becomes steeper, that is, there are more high-frequency components in the signal, which will also bring greater reflections in unmatched channels. There are still many particles in the entire topology, so although the channel matching is still good, the signal quality of the address line is not particularly good.

The second point: Due to the replacement of the board, compared with ordinary FR4, M6g has a

smaller loss value of DF from 0.02 to 0.004, and the attenuation of reflection is also reduced, resulting in some reflected energy accumulating more than ordinary boards, and the worse signal points will be aggravated. The simulation needs to take the board loss into account. The loss can attenuate the rising edge and the impact of attenuation reflections. Therefore, it is not that the DDR signal quality will be better if a better board is replaced. Different system environments may require detailed simulation to determine their signal quality.

The above are the problems that occur with the address lines. For the data signals, there is no need to worry too much about this problem. It has a one-to-one structure and ODT (On-Die Termination). There are few impedance mismatch points, and the topology is relatively stable relative to the address. The original eye diagram also has a large margin.