Is there any delay when directly connecting FPGA I/O pins?

book1

Is there any delay when directly connecting FPGA I/O pins? [Copy link]

If I connect any two I/O pins directly without a buffer in between, is there any delay? The delay of connecting one inverter in between and connecting three inverters should be 3 times different. Why are the delays in the simulation results the same? I am a novice, please help me, thank you! The system is set by default.

Jacktang

Explanation: There is a delay

It has something to do with the mode in which the I/O ports are assigned to pins.

cruelfox

External delays are not the responsibility of the simulation software. If you really want to consider delays, you need to give the delays yourself.

book1

cruelfox posted on 2021-5-13 10:30 External delay is not the responsibility of the simulation software. If you really want to consider the delay, you need to give the delay yourself.

It is a buffer or inverter inside the FPGA chip.

bqgup

It takes time for a signal to pass through a transmission line, and there is always a delay. The signal transmission is fast and the delay is very small. For example, if the RS485 and RS232 lines are too long, the signal cannot be transmitted, and communication is impossible beyond a certain distance.

heningbo

You are talking about logically implementing assign a=b;

Or connect the two PINs on the layout.

If it is a logical implementation, I generally don't consider delay.

If it is a layout issue, it depends on how long the line is, but generally only high-speed signals are considered.