How to deal with impedance continuity of PCB traces?

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How to deal with impedance continuity of PCB traces? [Copy link]

Everyone knows that impedance should be continuous. However, as Luo Yonghao said, "There are always times in life when you step on shit." There are also times when impedance is not continuous in PCB design. What should we do?

Characteristic impedance: Also known as "characteristic impedance", it is not DC resistance, but a concept in long-distance transmission. In the high-frequency range, when the signal reaches the place where the signal line reaches, an instantaneous current will be generated between the signal line and the reference plane (power supply or ground plane) due to the establishment of an electric field.

If the transmission line is isotropic, then as long as the signal is being transmitted, there will always be a current I. If the output voltage of the signal is V, during the signal transmission process, the transmission line will be equivalent to a resistor with a magnitude of V/I. This equivalent resistance is called the characteristic impedance Z of the transmission line.

During the transmission process of a signal, if the characteristic impedance on the transmission path changes, the signal will be reflected at the node where the impedance is discontinuous.

Factors that affect characteristic impedance include: dielectric constant, dielectric thickness, line width, and copper foil thickness.

【1】 Gradient line
Some RF device packages are small, the SMD pad width may be as small as 12 mils, while the RF signal line width may be more than 50 mils. Gradient lines should be used, and sudden changes in line width are prohibited. Gradient lines are shown in the figure, and the transition part of the line should not be too long.

[2]
If the RF signal line at the corner runs at a right angle, the effective line width at the corner will increase, the impedance will be discontinuous, and signal reflection will occur. In order to reduce the discontinuity, the corner needs to be processed. There are two methods: corner cutting and corner rounding. The radius of the arc angle should be large enough. Generally speaking, it should be ensured that: R>3W. As shown in the figure.

【3】Large pad
When there is a large pad on a 50 ohm microstrip line, the large pad is equivalent to distributed capacitance, which destroys the continuity of the characteristic impedance of the microstrip line. Two methods can be used to improve it at the same time: first, thicken the microstrip line dielectric, and second, hollow out the ground plane under the pad, both of which can reduce the distributed capacitance of the pad. See the figure below.

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【4】Via Vias
are metal cylinders plated outside of through holes between the top and bottom layers of a board. Signal vias connect transmission lines on different layers. Via stubs are unused portions of a via. Via pads are donut-shaped pads that connect vias to top or internal transmission lines. Isolation pads are annular gaps within each power or ground plane to prevent short circuits to the power and ground planes.

Parasitic parameters of vias

After rigorous physical theory derivation and approximate analysis, the equivalent circuit model of the via can be an inductor with a grounding capacitor connected in series at both ends, as shown in Figure 1.

Equivalent circuit model of vias

From the equivalent circuit model, we know that the via itself has parasitic capacitance to the ground. Assuming that the diameter of the via anti-pad is D2, the diameter of the via pad is D1, the thickness of the PCB is T, and the dielectric constant of the substrate is ε, the parasitic capacitance of the via is approximately:

The parasitic capacitance of vias can cause the signal rise time to be prolonged and the transmission speed to be slowed down, thus deteriorating the signal quality. Similarly, vias also have parasitic inductance. In high-speed digital PCBs, the harm caused by parasitic inductance is often greater than parasitic capacitance.

Its parasitic series inductance will weaken the contribution of the bypass capacitor, thereby weakening the filtering effect of the entire power system. Assume that L is the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole. The approximate parasitic inductance of the via is approximately:

Vias are one of the important factors that cause impedance discontinuity in RF channels. If the signal frequency is greater than 1GHz, the impact of vias must be considered.

Common methods to reduce the impedance discontinuity of vias include: using padless technology, selecting the routing method, optimizing the anti-pad diameter, etc. Optimizing the anti-pad diameter is one of the most commonly used methods to reduce impedance discontinuity. Since the characteristics of vias are related to the structural dimensions such as aperture, pad, anti-pad, stacking structure, routing method, etc., it is recommended to use HFSS and Optimetrics for optimization simulation according to the specific situation every time you design.

When a parametric model is used, the modeling process is simple. During the review, the PCB designer is required to provide the corresponding simulation documents.

The via diameter, pad diameter, depth, and anti-pad will all cause changes in impedance discontinuity, reflection, and insertion loss severity.

【5】Through-hole coaxial connectors
are similar to via structures. Through-hole coaxial connectors also have impedance discontinuity, so the solution is the same as that of vias. The common methods to reduce the impedance discontinuity of through-hole coaxial connectors are also: using a padless process, a suitable wiring method, and optimizing the anti-pad diameter.

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The routing is basically done directly on the signal line without destroying the impedance characteristics.