The basic structure and characteristics of DSP

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The basic structure and characteristics of DSP [Copy link]

Programming DSP chip is a microprocessor with a special structure. In order to achieve the purpose of fast digital signal processing, DSP chip generally adopts special software and hardware structure:

(1) Harvard structure.

DSP uses Harvard structure, which divides the memory space into two, storing programs and data respectively. They have two sets of buses connected to the processor core, allowing them to be accessed simultaneously, and each memory is independently addressed and accessed independently. This arrangement doubles the data throughput of the processor, and more importantly, provides data and instructions to the processor core at the same time. Under this layout, DSP can implement single-cycle MAC instructions.

In the Harvard architecture, since the program and data memories are in two separate spaces, instruction fetching and execution can run completely overlappingly.

(2) Assembly line.

Related to the Harvard structure, DSP chips widely use 2-6 pipelines to reduce instruction execution time, thereby enhancing the processing power of the processor. This allows instruction execution to be completely overlapped, and different instructions are active in each instruction cycle.

(3) Independent hardware multiplier.

In systems that implement multimedia functions and digital signal processing, algorithm implementation and digital filtering are both computationally intensive applications. In these cases, multiplication is an important component of digital processing and one of the basic elements for the implementation of various algorithms. The faster the multiplication is executed, the higher the performance of the DSP processor. Compared with general processors that require 30-40 instruction cycles, the feature of DSP chips is that they have a dedicated hardware multiplier, and multiplication can be completed within one cycle.

(4) Special DSP instructions.

Another feature of DSP is the use of special instructions, which are specially optimized for some common algorithms in digital signal processing. These special instructions provide acceleration for some typical digital processing, which can greatly improve the execution efficiency of the processor, making real-time data processing of some high-speed systems possible.

(5) Independent DMA bus and controller.

There are one or more independent DMA buses that work in parallel with the CPU's program and data buses. Without affecting the CPU's operation, the DMA speed has reached more than 800MB/S. This can reduce CPU overhead and increase data throughput when large amounts of data need to be exchanged, thereby improving the system's parallel execution capabilities.

(6) Multiprocessor interface.

It allows multiple processors to work in parallel or serially to increase processing speed.

(7) JTAG (Joint Test Action Group) standard test interface (IEEE 1149 standard interface).

It is convenient for on-chip online simulation of DSP and debugging under multi-DSP conditions.

(8) Fast instruction cycle.

Harvard structure, pipeline operation, dedicated hardware multiplier, special DSP instructions and optimized design of integrated circuits make the instruction cycle of DSP chips less than 10ns. The fast instruction cycle enables DSP chips to implement many DSP applications in real time.