What is the reason for the large power-on deviation of the data sent from the op amp sampling circuit to the DSP?

乱世煮酒论天下

What is the reason for the large power-on deviation of the data sent from the op amp sampling circuit to the DSP? [Copy link]

 

A low-value resistor sampling circuit, through an isolation op amp chip, amplified by a differential circuit, and then converted into a 0-3V analog signal through a bias circuit. The current detection fault will be reported as soon as the power is turned on again. The software engineer explained that when the power is not on, the current is zero, and the voltage sampled by the AD should be 1.5V, but now the fault occurs when the power is turned on. The deviation from the reference voltage is large, which may be less than 1V or greater than 2V. What is the reason? How to solve it? It did not report before when it was powered on, but this fault occurred after I modified the setting resistance of this differential circuit. Is it because the resistance is not suitable?

qwqwqw2088

Why did you change the resistor setting of this differential circuit?

Post the circuit diagram for everyone to analyze

maychang

[This fault occurred after I modified the setting resistance of this differential circuit. Is it because the resistance is not suitable? ]

I just dismantled and modified it randomly, and when it broke down I asked questions in the forum.

乱世煮酒论天下

qwqwqw2088 posted on 2024-9-10 17:32 Why did you "modify the setting resistance of this differential circuit"? Post the circuit diagram for everyone to analyze

The front stage is a linear optocoupler amplifier, and the setting resistors are these four resistors. The original ones were 5.1k and 16k, but now they are changed to 13k and 24k. The capacitors and others have not changed.

乱世煮酒论天下

maychang posted on 2024-9-10 18:06 [This fault occurred after I modified the setting resistor of this differential circuit. Is it because the resistor is not suitable? ] I just disassembled and modified it randomly, and after changing it...

Change the setting parameters, the power of the whole machine needs to be changed

qwqwqw2088

乱世煮酒论天下published on 2024-9-10 19:31 The front stage is a linear optocoupler amplifier. The setting resistors are these four resistors. The original ones were 5.1k and 16k, but now they are changed to 13k and 24k. The capacitors and other...

This is a random amplifier circuit.

This is different from "the power-on deviation of the op amp sampling circuit to the DSP is large".

"The software engineer explained that when the power is off, the current is zero and the voltage sampled by the AD should be 1.5V."

What does it matter?

maychang

乱世煮酒论天下published on 2024-9-10 19:31 The front stage is a linear optocoupler amplifier. The setting resistors are these four resistors. The original ones were 5.1k and 16k, but now they are changed to 13k and 24k. The capacitors and other...

[The setting resistors are these four resistors, originally 5.1k and 16k, now changed to 13k and 24k]

After changing the resistor, the voltage gain of the stage becomes much greater than before the change. Have you calculated it?

乱世煮酒论天下

qwqwqw2088 posted on 2024-9-10 19:40 This is a random amplifier circuit and "the operational amplifier sampling circuit is sent to the DSP for power-on with a large deviation." "Software Engineer Interpretation...

The previous stage current sampling is an AC signal with positive and negative, and it is still positive and negative at this stage. The next stage is the bias circuit, which is biased to 0-3V. The maximum positive phase is 3V and the maximum negative phase is -3V. The bias is 0-3V, and no current is 0V. The result of the bias is 1.5V

乱世煮酒论天下

maychang posted on 2024-9-10 19:41 [The setting resistors are these four resistors, originally 5.1k and 16k, now changed to 13k and 24k] After changing the resistors, the voltage gain and change of this level...

According to the circuit gain calculation, the low-value sampling resistor is 0.001Ω, the rated current is 25A, there is a first-level optocoupler chip to amplify 8 times, and then this op amp, just adjust the four setting resistors, the front 2K resistor remains unchanged, and the whole machine has been tested, the displayed current and the actual current are less than 1A

led2015

Try changing to resistors of different values, observe the changes in the output signal, and find the most suitable resistance value.

lansebuluo

Wouldn't it be clear if you use an oscilloscope? The information provided is not comprehensive, so why bother discussing it here?

yangjiaxu

Op amp offset voltage, power supply voltage fluctuation, temperature drift, input signal source impedance mismatch, and insufficient op amp gain-bandwidth product may all cause your problem.

qwqwqw2088

乱世煮酒论天下published on 2024-9-10 19:55 The previous stage current sampling is an AC signal with positive and negative, and it is still positive and negative at this stage. The next stage is the bias circuit, which is biased to 0-3V, and the maximum positive phase is 3V...

Use an oscilloscope to look at the output waveform of the bias circuit to ensure that it is stable at 1.5V when there is no signal, and can correctly follow the input signal when there is an input signal.

The bias circuit cannot accurately bias the signal to 1.5V. Is there a temperature drift problem?
Modifying the resistor value may change the gain or bias of the differential circuit.

It's all possible

qwqwqw2088

Then, work with your software engineer to check the AD sampling code in the software.

Adjust the resistance value, observe the change of AD sampling voltage, find the best setting, and ensure that it can correctly read and process the output value of the AD converter.

Gen_X

There is a large time difference between the power-on "zero point" and the steady-state zero point of this circuit. It is recommended that C1 be reduced to 51P or lower.

It seems that C1 and C2 are symmetrical, but actually C1 has a completely different role in the negative feedback loop, which will cause the transition time from the startup zero point to the steady-state zero point to increase a lot. Therefore, it is recommended that C1C2 be connected to the positive and negative inputs of the op amp to the ground, and C3 be added between them. If the amplification factor is not high, the capacitance at the C1 position should not be greater than 100P!!!

乱世煮酒论天下

Gen_X posted on 2024-9-13 16:20 There is a large time difference between the power supply "zero point" and the running steady-state zero point of this circuit. It is recommended to reduce C1 to 51P or lower. It seems that C1 and C ...

This is related to the system stability of the feedback control system. Does my circuit have overshoot? That is, there is a relatively large and long ringing. The time required for the system to return to a stable state is relatively long. There are problems of over-replication and long stabilization period. Therefore, the system's unit gain margin and phase margin need to be adjusted. Is this the principle?

Gen_X

Luan Shi Zhu Jiu Lun Tian Xia published on 2024-9-13 17:06 This is related to the system stability of the feedback control system. Does my circuit have overshoot, that is, there is a relatively large and long ringing, the system feedback...

That's right! Your C1 is usually between 3-20P, not this big.