Application and design overview of power line communication analog front end AFE031

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Application and design overview of power line communication analog front end AFE031 [Copy link]

Author: Luo Jialin, Intern Engineer, Pang Jiahua, South China Engineer email: pangjiahua@ti.com

AFE031 is an analog front-end device used in power line communication and can be used as a transceiver for power line communication systems. This article will introduce AFE031 from three aspects: application background, basic framework and system design.

1. Application Background

Power Line Communication (PLC) is a communication technology that uses power lines to transmit data information. Its basic system block diagram is shown in Figure 1. After being modulated, the digital signal is sent in the form of a carrier wave, and then conditioned by the PLC transceiver, it is loaded onto the power line for transmission, while reception is a reverse process. The SunSpec fast shutdown protocol is a PLC protocol specifically formulated for the fast shutdown function of photovoltaic systems. SunSpec stipulates that the modulation method uses B-FSK (binary frequency shift keying). The B-FSK modulation principle is shown in Figure 2. The two carrier frequencies specified by SunSpec are f _m =131.25kHz and f _s =143.75kHz, which are in the CENELEC B/C/D frequency band of narrowband communication. In addition, the two types of valid commands specified by SunSpec include shutdown commands and normal working commands. The complete transmission cycle of a command is 1070.08ms. For a detailed introduction to the FSK principle and SunSpec communication parameter regulations, please refer to TIDA-060001.

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Figure 1. PLC system block diagram

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Figure 2. FSK modulation principle

The PLC transceiver is composed of analog front-end devices, which condition the digital signal sent by the MCU or the carrier signal received from the power line to ensure that the signal can be accurately, effectively and reliably transmitted on the power line. The AFE031 is a high-quality PLC analog front-end device that can be used to build a PLC system that supports SunSpec and other protocols. Its interface with the MCU is shown in Figure 1.

2. AFE031 Basic Overview

AFE031 is highly integrated internally. Figure 3 is the functional block diagram of AFE031, where the red circle indicates the PLC Tx module, the blue circle indicates the PLC Rx module, and the purple circle indicates other auxiliary function modules. The internal resources are rich.

The Tx module is responsible for processing the transmission path signal, which includes a digital-to-analog converter DAC, an adjustable gain amplifier Tx_PGA, an adjustable bandwidth low-pass filter Tx_Filter, and a power amplifier PA. In the Tx module, the signal to be transmitted is amplified and filtered and then sent to the power amplifier PA. The PA further amplifies the signal with a fixed gain of 6.5V/V and outputs it to drive the load.

The Rx module is responsible for processing the receiving path signal. The links on the receiving path are gain adjustable amplifier Rx_PGA ₁ , bandwidth adjustable low-pass filter Rx_Filter, and adjustable gain amplifier Rx_PGA _2. After amplification and filtering, the received signal is sent to the ADC of the MCU to restore the digital signal.

The MCU can configure the AFE031 registers via the SPI interface to change the amplifier and filter parameters of the Tx and Rx modules. For SunSpec applications, the Tx and Rx filters can be set to CENELEC B/C/D, corresponding to a cutoff frequency of 145kHz. For more MCU and AFE031 interface methods and parameter adjustment methods, please visit SBOA130A and TIDA-060001.

The advantages of AFE031 can be summarized as follows: support for multiple protocols including SunSpec; wide power supply PA_Vs _range of 7-24V; output current up to 1.5A; good receiving sensitivity, capable of detecting signals as low as 20 μV _RMS ; highly integrated, rich in resources; and flexible configuration.

The above is a basic introduction to the basic framework of AFE031, the functions and advantages of the main modules. For detailed introduction to the parameter values, working principles and register configurations of each module, please refer to the AFE031 data sheet.

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Figure 3. AFE031 functional block diagram

3. Key points of SunSpec PLC system design based on AFE031

There are several parts to focus on when building a SunSpec PLC system based on AFE031: Tx path, Rx path, power line coupling circuit, and protection circuit. The following will introduce the key points of peripheral circuit design for these parts.

(1) Tx path

AFE031 supports two Tx modes, namely DAC mode and PWM mode. The connection methods and peripheral circuit designs of the two are different, as shown in Figure 4(a) and Figure 4(b).

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Figure 4. Tx path. (a) DAC mode, (b) PWM mode

Both modes require setting the PA input AC coupling capacitor C _IN and the PA current limit setting resistor R _SET . C _{IN is a high-pass filter, and its value is determined by the cutoff frequency} f _HP required by the user . The lower frequency f _m of SunSpec is 131.25kHz. In order to reserve a certain margin, f _HP should be set to be less than f _m . The calculation formula of C _IN is:

(1)

R _SET is connected in series to the PA_ISET pin. The relationship between R _SET and the current limit value I _{LIM is:}

(2)

The difference between the two modes is that in DAC mode, the MCU will send a sine wave discrete value to AFE031 through a fast interrupt. Although this process will occupy more CPU resources, the harmonic content of the transmitted signal after DAC conversion is very small, and there is no need to set too many peripheral filters; while in PWM mode, the MCU directly sends PWM waves to AFE031 through the peripheral ePWM. In this mode, the configuration of the MCU is very simple, but the harmonic content of the signal is large, and it is necessary to set up peripheral filters, such as the RC low-pass filters Fd1 and Fd2 shown in Figure 4(b) _, which _{can enhance the filtering of high-order harmonics of the PWM wave. The RC low-pass filter is recommended to use a resistor Rd of} 510Ω and _a cutoff frequency of fL , _{which should be greater than the frequency of} the signal to be transmitted. The maximum carrier frequency of the SunSpec protocol is fs =143.75kHz, so fL should be greater than _fs . The _{corresponding} settings _of Cd1 and Cd2 can refer to the following formula:

(3)

(2) Rx path

The Rx path is shown in FIG5 . In the Rx path, the received signal passes through the peripheral bandpass filter F1 and the internal Rx module of AFE031 in sequence.

Due to the complex working environment of the power line, the signal received by AFE031 may contain various interferences. Therefore, it is necessary to set an external bandpass filter F1 for the Rx path. F1 is a fourth-order bandpass filter. Its design can follow the following principles: First, select the filter characteristic impedance Zc , which matches the transmission line impedance. For PLC applications, it can be set to 1kΩ; then determine the resistance size. The two resistors _R1 and R2 play a voltage divider role. When R1 = R2 = Zc is selected, the signal has a -6dB attenuation. If R1 = Zc and R2 ₌ 10 Zc are _selected , _the signal has a gain close to 0dB ; _{finally ,} the remaining LC _{parameters can be determined} according to the following formula:

(4)

Where f1 is _the low frequency cutoff frequency of the bandpass filter, f2 is the high frequency cutoff frequency of the bandpass filter. For SunSpec applications, f1 should be less than fm , and _f2 should _be greater than fs . For example, you can choose _C1 = 1.7nF , _C2 = 1nF, _L1 = _1.2mH , L2 _{= 1.5mH .}

In addition, it should be noted that Rx_Filter is a unity-gain fourth-order low-pass filter that requires two external auxiliary capacitors to properly configure the filter. For the CENELEC B/C/D bands where SunSpec is located, the two capacitor settings are CR1 = 270pF and _CR2 = 560pF _.

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Figure 5. Rx path

(3) Power line coupling circuit

The power line coupling circuit is used to connect the AFE031 and the power line so that signals can interact between the two. The coupling circuits for AC power lines and DC power lines are different and need to be introduced separately.

a. Communication Application

For AC applications, the power line coupling circuit is shown in Figure 6, which includes a low-voltage side capacitor C _LV , a transformer T, a high-voltage side capacitor C _HV , and a high-voltage side inductor L _HV . The main function of C _LV is to isolate the low-voltage side bias DC voltage. The capacitor should present low impedance to high-frequency signals. A 10μF capacitor is commonly used, and its withstand voltage should be greater than the TVS clamping voltage value introduced later. C _HV and the transformer T winding inductor form a voltage divider. C _HV withstands the low-frequency AC high voltage V _AC , and the high-frequency signal is coupled to the low-voltage side through the transformer. The size of C _HV should be set according to the reactive power limit VA _limit :

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Where fP is the power frequency, and the withstand voltage of C _{HV should be higher than the power line voltage. However ,} the C _HV set according to VA _limit may bring a large impedance, resulting in insufficient ability to drive the load, so L _HV is needed to maintain low impedance of the power line. For SunSpec, the center frequency of the two carrier frequencies f _m and f _s can be considered to be f _b = 137.5kHz, so the value of L _HV can be determined :

(9)

As for the value of the turns ratio of the transformer T, it can be matched according to the load's requirement for obtaining the maximum output power of the PA. Assuming that V _{PA_out_peak} and I _{PA_out_peak} are the maximum output voltage and current of the PA, respectively, and the equivalent load on the high-voltage side is R _load , the turns ratio can be referred to the following formula:

(10)

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Figure 6. AC-coupled circuit.

b. DC applications

In low-voltage DC applications, transformers are not required. Only capacitor C _DC is used to couple the power line and the analog front-end circuit. As shown in Figure 7, the DC bus voltage is 24V generated by TPS43060, and the coupling capacitor C _DC is usually 10uF, and its rated voltage must be greater than the DC bus voltage. In addition, since the DC line is a low-impedance line and the output end of TPS43060 also has low impedance for high-frequency signals, the PA output signal may enter the DC power supply from the DC line and then be pulled down, which greatly affects the PA output swing. Therefore, it is necessary to connect an inductor L _DC in series on the power supply side to increase the power supply output impedance, such as 680uH in the figure, and the impedance to the SunSpec center frequency reaches 587Ω. It should be noted that this is a low-voltage DC occasion. Based on capacitor coupling, the ground on the power line side can be connected to the ground of AFE031 .

If it is used in high-voltage DC applications, direct connection between the two grounds should be avoided, and a transformer must be used for isolation and coupling. Please refer to the EVM board Boost-AFE031 block diagram shown in Figure 8.

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Figure 7. Low voltage DC coupled circuit.

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Figure 8. General DC-coupled circuit.

(4) Protection circuit

The following is an example of the protection circuit for DC applications. The protection circuit for DC applications is shown in Figure 9. The TVS tube is a transient diode to prevent the instantaneous large voltage from damaging the AFE031. The clamping voltage of the TVS should be slightly larger than PA_Vs _{/ 2 to improve the reliability of the protection under the premise of} ensuring no false triggering. The role of the Schottky diodes _D1 - D2 is to suppress the impact of continuous overvoltage on the AFE01. Since D1 - _D2 have junction capacitance, the imbalance of the junction capacitance will cause the DC bias to not be maintained at PA_Vs / ₂ . The role of the voltage divider _{Rb1 -} Rb2 is to improve this situation so that the PA output has the correct DC bias. The role of the voltage regulator Z is to stabilize the PA supply voltage PA_Vs of the AFE031 _. The L _o - C _o - R _o combination acts as an additional noise or ringing absorber. The empirical values selected are R _o =4.7Ω, C _o =1nF, and L _o =1mH.

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Figure 9. Protection circuit

4. Test results and summary

Based on AFE031, SunSpec PLC system was built for testing and verification. Figure 10 and Figure 11 are the instruction transmission waveform and the corresponding waveform spectrum when sending different carriers. It can be seen that the system can smoothly perform the SunSpec PLC communication function, and the harmonic content is small, ensuring the reliability of PLC communication.

As a PLC analog front-end device, AFE031 supports a variety of PLC protocols including SunSpec, and can easily realize reliable PLC communication functions. Its advantages also lie in its large power supply voltage range, large output current, and reception sensitivity that can detect signals as low as 20μVrms. When designing the system, the AFE031 registers can be configured through the SPI interface according to the selected communication method, and the peripheral filter parameters can be determined accordingly. Finally, the power line coupling circuit and necessary protection circuit can be added to complete the system construction.

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Figure 10. Transmission waveform experimental results

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Figure 11. (a) f _m carrier spectrum, (b) f _s carrier spectrum