A Silicon Valley chip company is recruiting in China, the work location is Shanghai; it needs an analog signal engineer, analog signal technology leader...

麦田2020

A Silicon Valley chip company is recruiting in China, the work location is Shanghai; it needs an analog signal engineer, analog signal technology leader... [Copy link]

A Silicon Valley chip company is recruiting in China and has received more than 40 million US dollars in investment from a well-known investment company;

Currently, we are planning to establish three R&D centers in Shanghai, Hangzhou and Suzhou.

Professor or student of MIT in the United States, so he has a strong R&D background

Currently recruiting for the following positions

1.

Senior Analog / Mixed Signal Engineer*1

Principle Analog/Mixed Signals Engineer

Job Description

Job ResponsibilitiesWhat he /she will do at LT?

CN Responsible for developing analog / mixed signal ( AMS) IP ( TIA , DAC/ADC, bandgap, LDO) specifications in consultation with system architect / line manager ; Responsible for the specific architecture selection and design of A MS IP ; Assign modules to team members and complete the design with the team ; Work with the layout team and coordinate communication between the layout team and designers ; Coordinate the documentation of AMS IP and its integration on SOC ; Coordinate with package /PCB/ digital teams to design test plans. EN

Job RequirementsPreferred Qualifications

CN Analog / mixed circuit design engineer with more than 8 years of industry experience Proficient in the working principle, design techniques and key parameters of high-speed analog circuits, including but not limited to TIA , DAC/ADC, BANDGAP, LDO, OPAMP, COMPARATOR, SERDES, PLL, DLL ; Familiar with deep submicron CMOS technology, multiple successful tape-out experiences, and complete product experience; Familiar with IC design and development process, and proficient in using common EDA development tools; Proficient in using common test instruments (oscilloscope, spectrum analyzer, network analyzer, etc.); Possess independent problem-solving ability, good communication skills and cooperative attitude . EN

2.

Analog / Mixed Signal Engineer*2

Analog/Mixed Signals Engineer

Job Description

Job ResponsibilitiesWhat he /she will do at LT?

CN Assist line manager to develop analog / mixed signal ( AMS) IP (TIA, DAC/ADC, bandgap, LDO) specifications; Assist in the specific architecture selection and design of A MS IP ; Independently undertake corresponding modules and work with the team to complete the design; Work with the layout team and coordinate communication between the layout team and designers ; Coordinate the documentation of AMS IP and its integration on SOC ; Coordinate with package /PCB/ digital teams to design test plans.

Job RequirementsPreferred Qualifications

CN Analog / mixed circuit design engineer with more than 2 years of industry experience Proficient in the working principle, design techniques and key parameters of high-speed analog circuits, including but not limited to TIA, DAC/ADC, BANDGAP, LDO, OPAMP, COMPARATOR ; Familiar with deep submicron CMOS technology, multiple successful tape-out experiences, and complete product experience; Familiar with IC design and development process, and proficient in using common EDA development tools; Proficient in using common test instruments (oscilloscope, spectrum analyzer, network analyzer, etc.); Possess independent problem-solving ability, good communication skills and cooperative attitude .

3. Senior layout engineer

Job Description

Job ResponsibilitiesWhat he /she will do at LT?

EN Senior layout designer to work with analog design engineers to perform layout for high speed, high performance analog/mixed signal circuits (TIA, DAC/ADC, etc.) at the block and full chip level in advanced Foundry CMOS process Work closely with design lead and physical designers for top level floor planning and integration of analog IPs with the SOC system Establish the layout procedures and best practices within the company while helping to build up the layout team

Job RequirementsPreferred Qualifications

EN 5+ years' experience in high performance analog layout in advanced CMOS process (28nm or smaller geometry CMOS, deep metal stack, high frequency design >1 GHz) Experience with layout of high-performance analog IP blocks such as TIA , DAC/ADC, etc. highly desired Thorough knowledge with industry standard EDA tools such as Cadence Virtuoso; extensive experience with DRC, LVS tools and debug verification process Experience with floor planning, block level routing and top level chip assembly Knowledge of high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices Experienced in robust power/signal routing and EM analysis Strong communicator, works well independently and in team situations Experience in working with distributed design teams a plus

Company benefits: basic salary*16+options

Welfare: five insurances and one fund, lunch, etc.

In addition, as a R&D staff, we have the opportunity to go to the United States for half a year every year for study and exchange. The overall atmosphere of the company is very technical.

Junior R&D can be led directly by MIT Fellows, so they have the opportunity to learn good technical theories from the beginning;

If you want to join, please send your resume to John.zhou@talent-sea.cn (note: from Electronic Network)

Or WeChat: zoopu2013