Internal bus block diagram of DM644x Davinci processor

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Internal bus block diagram of DM644x Davinci processor [Copy link]

The master device initiates data transmission

　　The slave device can only transfer data according to the command, but the slave device can initiate the transfer by sending a transfer request interrupt to the CPU or EDMA3;

　　C64x on-chip storage

　　TI C6000 series DSP on-chip bus architecture, storage system and peripherals

　　Figure 1 C64x on-chip storage

　　L1P Cache Controller

　　Direct Mapped (1 way)

　　Same frequency as CPU, size is 16KB, each cache line size is 8 instructions, i.e. 32 bytes

　　L1D Cache Controller

　　2-way Cache

　　Same frequency as CPU, size is 16KB, each cache line size is 64 bytes

　　L2 RAMs, Cache Controller

　　C6414/15/16 = 1M Byte

　　C6411/DM642 = 256K Byte

　　The C64x+ adds an IDMA unit to transfer data between the above three internal memories, and can also store data from the chip to the config register.

　　C6000 Series DSP Peripherals

　　TI C6000 series DSP on-chip bus architecture, storage system and peripherals

　　Figure 2 C6000 series DSP peripherals

　　EDMA3 Controller

　　DMA can complete data transfer between memories or from memory to peripherals, or from peripherals to memory. It can be driven by external device events to synchronize data and can handle up to 64 events. Both DSP and ARM can access DMA channel resources, but for IDMA added from C64x+, only DSP can access its channel resources.

　　There is also a QDMA channel (Quick DMA) that can perform DMA transfer between memories. It must be processed asynchronously, that is, it must be initiated by the CPU. A general DSP will have 4-8 QDMA channels.

　　These DMA channels share some resources, including 128-256 parameter RAM sets (PARAMs), 64 transfer completion flags (TCCS) and 2-4 transfer suspension queues.

　　Main peripherals

　　VPSS (and other master devices)

　　USB, ATA, Ethernet, and VLYNQ will share access to the SCR;

　　PRU (Programmable Realtime Unit) controller

　　TI C6000 series DSP on-chip bus architecture, storage system and peripherals

　　The PRU includes two independent real-time RISC cores (only about 40 instructions, performing logic, arithmetic and process control, etc.), which can be software-programmed to implement peripherals and access GPIO pins. The PRU also has its own interrupt controller and can access memory through the SCR. It can also perform power management control, such as shutting down the ARM or DSP, and shutting down or waking up the processor as much as possible according to system events.

　　Pin multiplexing means defining pins through programming to implement the peripherals you need.

　　Multi-channel buffered serial port McBSP (MulTI-Channel Buffered Serial Port)

　　2/3 full-power synchronous serial ports;

　　The maximum speed can reach 100Mbps

　　Support SPI bus protocol

　　Supports multiple channel processing (T1, E1, MVIP, ...)

　　Multi-channel audio serial port McASP (MulTI-Channel Audio Serial Port)

　　Supports up to 8 stereos (16 channels)

　　I2C support

　　A single SPI or I2C device;

　　SRIO（Serial Rapid IO）

　　High-speed serial transmission, such as the C6455 device supports 4 SRIO interfaces, which can be used for chain connection communication; the data transmission speed of each interface reaches 3.25Gbps (enough to support 1080P HD video), and can be connected to the SRIO switch, hub and FPGA for high-speed data transmission.

　　Clock and counterTimer / Counter

　　32-bit timer/counters can be used to generate interrupts;

　　64-bit timers/counters can be used to evaluate the algorithm;

　　Ethernet EMAC

　　10/100 Ethernet MAC, PIN and PCI multiplexing;

　　TCP/IP protocol stack is provided by TI NDK

　　Some newer devices support 10/100/1000 Ethernet MAC

　　Video Ports (DM series DaVinci processors)

　　Used for video image acquisition and display;

　　Two 8/10-bit BT656 or raw RGB modes;

　　16/20-bit raw mode or 20-bit Y/C mode for HD applications

　　Supports 8-bit line scaling and chroma resampling