MSP430 CPU and MSP430X CPU

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MSP430 CPU and MSP430X CPU [Copy link]

MSP430 CPU refers to the 16-bit CPU used in the MSP430F1xx series, with a data bus width of 16 bits, an address bus width of 16 bits, and a register of 16 bits. The addressing space is 216=64KB.
MSP430X CPU (abbreviated as CPUX) refers to the CPU used in the MSP430F2xx/4xx/5xx/6xx series, with a data bus width of 16 bits, an address bus width of 20 bits, and a register of 20 bits. The addressing space is 220=1MB. The arithmetic logic unit (ALU) of CPUX can also perform 20-bit calculations.
CPUX is backward compatible with MSP430 CPU

PC, SP, SR
PC:
After fetching an instruction, the CPU automatically increments the PC according to the number of bytes in the instruction, so the value of the 20-bit PC (R0) always points to the next instruction to be executed. PC always points to an even address (bit0 = 0).
SP:
20-bit stack pointer, always points to an even address
[Function]: protect the current address and restore the current address.
First-in-last-out There
are two types of stacks:
(1) Upward growth, the bottom of the stack occupies the lower address, the top of the stack occupies the higher address: 8051
(2) Downward growth, the bottom of the stack occupies the higher address, the top of the stack occupies the lower address: MSP430, AVR
(3) ARM supports two types of stack growth.
SR:
The 16-bit status register (SR, also called R2) used as a source or destination register can only be used in register mode addressed by word instructions. The remaining combinations of addressing modes are used to support constant generators.
SCG1: System Clock Generator 1 This bit can be used to enable or disable functions in the clock system according to the device family; for example, DCO bias enable or disable.
SCG0: System Clock Generator 0 This bit can be used to enable or disable features in the clock system depending on the device family; for example, FLL (Frequency Locked Loop) is enabled or disabled.
OSCOFF: Oscillator Off. When this bit is set to 1, it turns off the LFXT1 crystal oscillator when the LFXT1 CLK is not used for MCLK or SMCLK.
CPUOFF: CPU Off. When this bit is set to 1, it turns off the CPU.
The CPUOFF, OSCOFF, SCGO, and SCG1 bits request that the system enter a low-power mode.
[Example]: Turn off and on the frequency locked loop (FLL)
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_3; // Set RSELx for DCO = 4.9 MHz
UCSCTL2 = FLLD_1 + 74; // Set DCO Multiplier for 2.45MHz
// (FLL_N + 1) * FLLRef = FdcoCLKDIV
// (74 + 1) * 32768 = 2.45MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop

//The __bis_SR_register() function sets the corresponding position in the SR register to 1.
//The __bic_SR_register() function sets the corresponding position in the SR register to 0.