IIC Protocol Analysis

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IIC Protocol Analysis

1. Protocol Basics
   1. Protocol Introduction

IIC-BUS (Inter-Integrated Circuit Bus) was first developed by PHilip Semiconductor (now acquired by NXP) in 1982. It is mainly used to facilitate data transmission between microcontrollers and peripheral devices. It is a half-duplex, two-wire serial transmission bus consisting of SDA (data) and SCL (clock).

The latest version of the protocol is the 2014 version, the official link is as follows:

https://www.nxp.com/docs/en/user-guide/UM10204.pdf

1. 2. Physical signal

Figure 1-1 Actual waveform of IIC

Figure 1-2 Basic form of IIC protocol

IIC consists of a clock line and a data line. Figure 1-1 shows the actual signal captured by an oscilloscope, and Figure 1-2 shows the basic form of IIC protocol data transmission.

The input and output structure of IIC adopts an open-drain structure. The open-drain structure cannot obtain a high level autonomously, so an external pull-up resistor Rp is required to achieve a high level during IIC communication. The size of Rp depends on the current sinking size of IIC in different modes.

Figures 1-3 and 1-4 describe the scenarios of IIC obtaining high and low levels. Because multiple devices may be connected to an IIC bus at the same time, it is easy to cause a short circuit if IIC uses push-pull output. IIC devices can control the level of the output signal by controlling the switch of the N-MOS tube. When the MOS tube G is at a low level, the MOS tube is cut off and the IIC bus is at a high level due to the presence of a pull-up resistor; when the MOS tube G is at a high level, the MOS tube is turned on, and the IIC bus is equivalent to being directly grounded at a low level.

The input of IIC transfers data to the input data register through a TTL Schottky trigger, and then provides it to the processor for processing.

Figure 1-3

Figure 1-4

IIC level standard:

Since all kinds of devices may be connected to the IIC bus, such as CMOS, NMOS, etc., the standards for high and low levels of IIC are not fixed. The values of high and low levels are 0.7V _DD and 0.3V _DD respectively .

Figure 1-5

1. 3. Bus connection

Figure 1-6

The clock line of IIC is always controlled by the host. The data transmission between the host and the slave is completed only on the SDA line. Data cannot be sent and received at the same time, so IIC is a half-duplex communication protocol. Multiple devices can be mounted on an IIC bus, and each device has its corresponding device address. Data transmission between devices can only be transmitted by one device to the device with the corresponding address.

Dream Source Technology

Figure 1-7

The IIC bus connection can accept a multi-host mode, that is, multiple devices can be used as hosts on an IIC bus, but only one device can be used as a host during a data transmission. Who is the host on an IIC bus depends on who controls the clock and data signals on the bus. As shown in Figure 1-7, multiple devices are mounted on this IIC bus, of which MCU1 and MCU2 can both be used as hosts, but there cannot be two hosts at the same time.

If two MCUs initiate a start signal at the same time (both try to become the host), the IIC arbitration mechanism will come into play to determine who becomes the host.

Figure 1-8

The arbitration mechanism of IIC benefits from its open-drain input and output structure. For example, as shown in Figure 1-8, when there are multiple devices mounted on the SCL line, and the SCL output of MCU2 is low, then the SCL of this IIC bus will be pulled low by MCU2, which is the "AND" feature.

The arbitration on IIC is mainly composed of two parts: SCL clock synchronization and SDA line arbitration.

Figure 1-9

As shown in Figure 1-9, CLK1 and CLK2 are clock signals generated simultaneously by devices connected to one SCL line. Due to the "AND" characteristic of the IIC bus, the parts with the same high level of the two devices form the final clock of SCL, that is, the clocks on the same IIC bus are the same.

Figure 1-10

Similarly, SDA arbitration is also based on the "AND" feature. As shown in Figure 1-10, when two devices send out start signals at the same time to transmit data, the data of DATA1 and DATA2 are the same in the first and second cycles, and then the two continue to transmit data. When the data of DATA2 is inconsistent with that of SDA in the third clock cycle, device 2 will stop sending data and start receiving mode instead. In this way, the data of SDA will be consistent with the data of DATA1, and the data of SDA will not be affected by the stop of device 2 sending data.

2. Protocol Specification
   1. Coding Rules

Start and stop conditions: The start signal of IIC is when the clock signal line (SCL) is at a high level, the data line (SDA) produces a falling edge, and the stop signal is when the clock signal line (SCL) is at a high level, the data line (SDA) produces a rising edge.

Figure 2-1

Acknowledge bit, non-acknowledge bit: When the host finishes transmitting 8 bits of data, the host will pull the SDA line high. At this time, if the slave receives the data correctly, it will pull SDA low and keep it low when SCL is high. This signal is the ACK signal. If the slave does not pull SDA low after transmitting 8 bits of data, the signal is NACK. If NACK appears, it means that the data transmission is wrong.

Figure 2-2

Data validity: When the clock signal is at a high level, the signal on the data line needs to remain unchanged. That is, when the clock line is at a high level, if there is a rising or falling edge on the data line, a stop and start signal will be generated, resulting in data transmission errors.

Figure 2-3

Byte organization: Data transmission on SDA is in units of 8 bits, i.e. one byte. There is no limit on the number of bytes transmitted each time. Each byte transmission must be followed by an acknowledge bit.

Let's take 01001001 (0X49) as an example, and its timing diagram is as follows:

Figure 2-4

1. 2. Signal Transmission

Each device on the IIC bus has a unique address corresponding to it, and when the signal is transmitted, the device is found according to the specified address to transmit the signal.

Write operation : After the host determines the device address of the slave, it generates a start signal and then sends the device address and read/write direction flag to the IIC bus. After the slave detects that the address corresponds to its own device address, it replies to the host with an acknowledgement signal. After receiving the acknowledgement signal, the host starts to send data to the device in bytes, and each byte is followed by an acknowledgement signal from the slave until the host sends the last data and generates a stop signal to end the data transmission.

Figure 2-5

Read operation : The read operation is somewhat similar to the write operation. It is also necessary to determine the address of the slave device to be read. Then the host generates a start signal and sends the address of the slave device and the instruction to read data to the IIC bus. After the slave device receives the address and finds that it matches its own, it will generate a response signal. At this point, the slave device starts to send the data that the host wants to read to the host. After the host correctly receives the data, it will reply with a response signal to the slave. When the host wants to end the read operation, the host will reply with a non-response signal and then generate a stop signal to end the data reading.

Figure 2-6

1. 3. Transfer Example

Figure 2-7

As shown in Figure 2-7, this is the IIC signal collected by the oscilloscope. Through our own observation, we get the information contained in this IIC segment. The host writes 0X0C to the device with address 0XA0.

Through the oscilloscope we can observe the true appearance of the IIC signal, but we can also realize that the oscilloscope has many inconveniences in the process of analyzing digital signals.

1. Oscilloscope analysis channels are relatively few:

Generally, the oscilloscopes we use are dual-channel, and the IIC bus happens to consist of only two wires. However, when the digital signal we need to measure is composed of multiple wires (such as spi), it is not convenient for us to use a two-channel oscilloscope.

2. The storage depth of the oscilloscope is relatively small: Generally speaking, the storage depth of the oscilloscope is limited, which is closely related to the storage depth and the sampling rate and sampling duration:

Memory depth = sampling rate x display time

Then, according to the principle of the above formula, the storage depth of the oscilloscope is certain. If we want to set a higher sampling rate, we will not be able to display a longer waveform, as shown in Figure 2-8. If we want to get a long enough waveform, the sampling rate will be insufficient, as shown in Figure 2-9.

Figure 2-8

Figure 2-9 Low sampling rate

3. No protocol decoding function :

As shown in Figure 2-7, the waveform captured by the oscilloscope is only a bare waveform. We need to enlarge the waveform and carefully identify it to obtain the information.

Figure 2-10 Logic analyzer decoding results

Compared with oscilloscopes, logic analyzers can better assist engineers in capturing and identifying digital signals. As shown in Figure 2-10, logic analyzers have a decoding function, which can automatically help engineers read the data. The number of channels of a logic analyzer is generally more than 16, and in terms of storage depth, a logic analyzer is much greater than an oscilloscope, so it can record very long data.

3. Logic Analyzer Preparation

For details on using the logic analyzer, please refer to: https://www.dreamsourcelab.com/doc/DSView_User_Guide.pdf

1. 1. Device connection and status check

The logic analyzer has a type-c interface. Use the correct connection cable to connect the logic analyzer to the USB interface of the computer (if the logic analyzer supports USB 3.0 interface, connecting to USB 2.0 interface will affect its maximum speed). Be sure to wait until the logic analyzer indicator light turns green and the software shows the correct instrument device, then you can correctly operate and use the logic analyzer.

Figure 3-1

1. 2. Signal connection under test

After the USB is connected normally, the logic analyzer will light up green, and then insert the cable into the detection channel of the logic analyzer. The four channels of the cable are divided into a group. The basic version of the device has 4 channels with a ground wire, and the enhanced version has each channel with a ground wire. Since the IIC rate is generally small, we only need to connect two channels and a common ground wire.

Figure 3-2

4. Waveform capture and protocol analysis
   1. Collection Settings

Acquisition duration, sampling rate: Regarding sampling rate and sampling duration, we need to understand that they are both related to storage depth. Storage depth = sampling rate * window display duration

The transmission rate of IIC bus is generally several hundred KHZ, and we only need to set the transmission rate to a few MHz. Here we use a sampling rate of 4MHz to sample IIC. The longest sampling time of the logic analyzer is different at different sampling rates. DSView will calculate the longest acquisition time based on the sampling rate you set. You can choose the corresponding sampling time according to your data volume.

Figure 4-1

Operation mode and threshold: The operation modes of the logic analyzer in DSView for capturing signals are stream and buffer modes. In stream mode, different numbers of channels have different maximum sampling rates, while in buffer mode, the maximum sampling rate is fixed. In addition, since the stream mode uses the PC's memory, it has a long sampling depth. The voltage threshold of DSView can be set between 0 and 5V . For a normal 3.3V digital system, we can set the threshold voltage to 1.0V . If it is set too low or too high, the signal will be inaccurate.

Figure 4-2

It should be noted here that DSView cannot perform advanced triggering in stream mode, but only some simple triggering. If you need to use a logic analyzer to capture specific data, you need to adjust the operating mode to buffer mode.

Figure 4-3

1. 2. Trigger condition setting and acquisition

Simple trigger: Simple trigger can capture signals by setting the trigger condition of a certain channel. As shown in Figure 4-4, we set the trigger condition to when channel 1 generates an edge signal, and it will be triggered when channel 1 generates a rising edge or a falling edge.

Figure 4-4

Acquisition : DSView can achieve immediate and normal capture. Immediate capture can be understood as immediately grabbing the current IIC signal without considering the trigger conditions. When your IIC signal is short and the sampling time you set is short, you may not be able to capture the waveform.

Normal capture can be entered by simply clicking the Start button (or pressing the S key on the keyboard). Normal capture can respond to trigger conditions and can set the acquisition mode.

Figure 4-5

DSView runs single acquisition and repeated acquisition. Single acquisition only allows you to acquire once and then stops. Repeated acquisition is to complete one acquisition and wait for a response time interval before restarting the acquisition and repeating this cycle. As shown in Figure 4-6, we can set the interval acquisition time, the setting range is 1 ~ 10S .

Figure 4-6

1. 3. Waveform viewing and measurements

Zoom: The waveform can be zoomed in and out by using the mouse wheel. You can also zoom in and out by using the left and right keys on the keyboard. You can also zoom in and out the waveform details by right-clicking the waveform (right-clicking can only zoom in and not shrink the waveform).

Figure 4-7 Right click to enlarge

Move: Press and hold the left mouse button to move the waveform left or right.

Frequency measurement: Simply move the mouse to the center of the waveform to calculate the frequency, period and other information of the signal.

Figure 4-8 Mouse detection frequency

Cursor application: When your waveform is too long to be fully displayed in the window, we can use the cursor to mark the place you want to observe and then jump the waveform position according to the cursor. Double-click on the waveform to add a cursor, and the number of cursors that can be added is unlimited. When you want to jump to a position, just right-click the cursor and the corresponding serial number will appear, and then directly click the serial number to jump to the corresponding cursor.

Figure 4-9 Cursor jump GIF image

1. 4. Protocol addition and decoding analysis

The signals on the IIC bus we collected are two waveforms, which are relatively rigid and not conducive to our understanding of the information contained in them. At this time, we need to use the decoding function contained in DSView. The decoding function can show the content contained in the IIC protocol in an intuitive form, which is convenient for our analysis.

Step 1: Click Decode on the menu bar and a window for adding a decoding protocol will appear on the right side of the DSView interface.

Figure 4-10

Step 2: Select the IIC protocol in the window that appears on the right, and then click the plus sign to add the protocol.

Figure 4-11

Step 3: After clicking the plus sign, an IIC protocol will appear below. Click the setting button (gear) on the left to enter the decoding settings window.

Figure 4-12

Step 4: First, set the displayed content. We can set it according to our own needs. Then the most important thing is to correspond the channel of the collected IIC to SCL and SDA. The slave address can be displayed as a package that does not contain read and write bits. Finally, the decoding area can be set to start to end, so that all the collected data will be decoded. If you want to decode a specific area, you can add two cursors and set the decoding area between these two cursors.

Figure 4-13

Step 5: Result Analysis

Figure 4-14

As shown in Figure 4-14, we set the decoding interval to the area between cursor 1 and cursor 2. This IIC timing sequence means reading data from the internal address 0X15 in the device with address 1010000, and the read data bit is 0X54.

5. Advanced Analysis

5.1. Collection techniques

Cyclic acquisition: When you need to observe a specific signal, it may be inconvenient to use a single operation. For example, different buttons represent different information, so we can set up cyclic acquisition to capture the button information.

Figure 5-1

Trigger positioning: If we want to observe a complete waveform, we can adjust the trigger position to the front (1%) or the back (90%). In this way, we can observe the waveform before and after the trigger, as shown in Figure 5-3.

Figure 5-2

Figure 5-3

5.2. Advanced triggering

Advanced triggering can be used in DSView to analyze the content of the transmission.

Step 1: First, you need to select the advanced trigger option in the trigger settings.

Figure 5-4

Step 2: Set the trigger position. The trigger position can be set at any position according to your needs. The trigger position determines the percentage of the signal you want to capture in the total signal you want to capture. When setting, you only need to fill in the value or drag the position bar with the mouse.

Figure 5-5

Step 3: Select serial trigger. IIC is a serial communication method, so we choose serial trigger. The total trigger level above is only used in multi-level triggering.

Figure 5-6

Step 4: Set the start and stop conditions and clock settings.

First, you need to match the channel with the IIC line you are testing, for example, channel 0 corresponds to SCL, and channel 1 corresponds to SDA. The start condition of IIC is that SDA generates a falling edge when SCL is high, and the stop condition is that SDA generates a low level when SCL is high, so the start condition and stop condition are set as shown on the left side of Figure 5-7. The clock setting is used to define the moment of clock sampling. Generally, we can set it to rising edge sampling.

Figure 5-7

Step 5: Set the data channel, data width, and data value

The data channel refers to which channel SDA is connected to. Here we are connected to channel 1. Since one response bit is required for each byte of data transmitted in the IIC protocol, the data width is set to 9. For example, if I set it to trigger when the data 0X57 appears, the data value should be 010101110, and the last bit is the response bit.

Of course, if we do not need to capture specific data, the data value, data bit width, and data channel do not need to be set.

Figure 5-8

Step 6: View the data

The results captured by the logic analyzer will be displayed on the main interface, and the trigger position is the location of the data we want to obtain.

We can also use list query to grab the location of this string of data. As shown in Figure 5-10, enter the data to be queried and click on the data to quickly locate the data in the main interface.

Figure 5-9

Figure 5-10

5.3.Stack High-level Protocol Analysis

Slightly more complex protocols will adopt a layered structure. For example, the read and write operations of EEPROM using IIC are based on the traditional IIC, but it also contains more meanings.

We demonstrate the high-level protocol parsing process of Stack by operating EEPROM

Steps:

1. Select "1: IIC". The IIC protocol adds "1: IIC" but cannot add "0: IIC". "0: IIC" cannot display multiple layers of protocols.

Figure 5-11

(2) Click "Multi-layer Protocol"

Figure 5-12

(3) Add the corresponding EEPROM protocol

Figure 5-13

4. Get the result

From the results, we can see that these five layers of decoding describe the meaning of IIC protocol communication from each bit to the whole in great detail.

Figure 5-14

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