【Project source code】Design of XPT2046 touch controller based on FPGA
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This article and design code were written by FPGA enthusiast Xiao Meige. Without the author's permission, this article is only allowed to be copied and reproduced on online forums, and the original author must be indicated when reprinting.
XPT2046 is a 4-wire resistive touch screen controller designed for mobile phones, personal digital assistants, portable devices, payment interrupt devices, touch screen displays and other devices. The chip is essentially a multi-channel ADC + voltage output chip. By applying voltage to two different sets of electrodes of the resistive touch screen at different times, and then measuring the voltage value on the other set of electrodes, the X or Y position coordinates of the touch point are obtained, and then provided to the processor for processing.
Introduction to resistive touch screen The
four-wire resistive touch screen is mainly composed of two layers of thin film coated with ITO. One layer has a vertical bus on the left and right edges of the screen, and the other layer has a horizontal bus at the bottom and top of the screen. If a voltage is applied to the two buses of a thin film, a uniform electric field will be formed on the ITO coating. When the user touches the touch screen, the two layers of film will contact at the touch point, and the voltage value of the contact point can be measured on the other layer of film.
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To measure in the X-axis direction, bias the left bus to 0V and the right bus to VCC. Connect the top or bottom bus to the ADC, and make a measurement when the top and bottom layers are in contact.
To measure in the Y-axis direction, bias the top bus to VCC and the bottom bus to 0V. Connect the ADC input to the left or right bus, and measure the voltage when the top and bottom layers are in contact.
As shown in the figure below, the measured voltage value is linearly related to the position of the contact point, that is, the X and Y coordinates of the contact point P can be calculated from VPX and VPY, respectively.
In actual measurement, the control circuit will alternately apply VCC voltage to the X and Y electrode groups to measure the voltage and calculate the coordinates of the contact point. Take the measurement process as an example:
the first step is to apply VCC to X+ and 0V to X-, measure the voltage value VPX on the Y+ (or Y-) electrode, and calculate the X coordinate of the contact point P; the
second step is to apply VCC to Y+ and 0V to Y-, measure the voltage value VPY on the X+ (or X-) electrode, and calculate the Y coordinate of the contact point P; the
above two steps constitute a measurement cycle, and a set of (X, Y) coordinates can be obtained.
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Figure 2.1: Schematic diagram of the working principle of the touch screen
Resistive touch screen controller XPT2046Through
the above introduction, it can be known that in order to realize the coordinate measurement of a certain touch point, it is necessary to apply voltage to the two layers of conductive film of the resistive touch screen module in a time-sharing manner. When applying voltage to the electrode of one of the conductive films, use ADC to measure the voltage on the electrode of the other conductive film. It can be seen that the touch controller must be able to support two functions:
the touch controller can apply voltage to the connected electrodes The touch
controller can measure the voltage on the electrode (ADC)
, that is, the touch controller is not just a simple ADC, because it must also be able to provide voltage to the electrode, so we cannot use a general ADC to complete the control of the 4-wire resistive touch screen. In order to realize the control of the resistive touch screen, many manufacturers represented by TI have launched dedicated touch controllers, such as TI's TSC2046 and ADS7843. The two have the same functions and compatible packages and can be directly replaced. At the same time, domestic manufacturers have also launched fully compatible devices, the most typical of which is the XPT2046 launched by Shenzhen Sipute Company. This chip is fully compatible with TI's TSC2046 device. This tutorial is mainly based on this chip for explanation.
XPT2046 features:
Operating voltage range is 2.2V ~ 5.25V
Support 1.5V ~ 5.25V digital I/O port
Built-in 2.5V reference voltage source Power
supply voltage measurement (0V ~ 6)
Built-in junction temperature measurement function
Touch pressure measurement
Use SPI 3-wire control communication interface
With automatic power-down function
Package: QFN-16, TSSOP-16 and VFBGA-48
Fully compatible with TSC2046 and AK4182A
XPT2046 consumes only 750 W at 125KHz conversion rate and 2.7V voltage. XPT2046 is widely used in small battery-powered handheld devices such as PDAs and mobile phones due to its low power consumption and high speed. The
following figure is a functional block diagram of XPT2046. It can be seen that XPT2046 contains a multiplexer inside, which can measure battery voltage, AUX voltage, and chip temperature. A 12-bit ADC is used to perform analog-to-digital conversion on the selected analog input channel to obtain digital values, which are then sent to the control logic circuit for reading by the main control CPU. At the same time, the specific channel to be converted is also set by the main control CPU sending commands to the control logic
.
XPT supports pen interrupts, that is, when the touch screen detects that the touch is pressed, a pen interrupt can be generated immediately to notify the main controller to control the start of conversion and read data. During the conversion process, the busy signal indicates the current busy state to avoid the main controller issuing a new command to interrupt the previous command.
XPT2046 pin
XPT2046 communicates with the main controller through the SPI interface. Its interface with the main controller includes the following signals:
PENIRQ_N: pen interrupt signal. When the pen interrupt signal is set to be valid, this pin is pulled to a low level every time the touch screen is pressed. When the main controller detects this signal, it can disable the pen interrupt by sending a control signal to avoid false triggering of the controller interrupt during the conversion process. A 50K pull-up resistor is connected to this pin.
CS_N: chip selection signal. When CS_N is pulled low, it is used to control the conversion timing and enable the serial input/output register to shift out or shift in data. When this pin is high, the chip (ADC) enters power-down mode.
DCLK: external clock input, which is used to drive the conversion process of the SAR ADC and drive serial data transmission on the digital IO.
DIN: Data serial input pin of the chip. When CS is low, data is latched into the register on the chip at the rising edge of the serial clock DCLK.
DOUT: Serial data output. Data is shifted out of this pin at the falling edge of the serial clock DCLK. When the CS_N pin is high, this pin is in high impedance state.
BUSY: Busy output signal. When the chip receives the command and starts the conversion, this pin generates a high level of one DCLK cycle. When the pin changes from high to low, the highest bit of the conversion result is presented on the DOUT pin, and the master can read the value of DOUT. When the CS_N pin is high, the BUSY pin is in high impedance state.
XPT2046 Working Principle
XPT2046 is a typical successive approximation analog-to-digital converter (SAR ADC), which includes sampling/holding, analog-to-digital conversion, serial port data output and other functions. At the same time, the chip integrates a 2.5V internal reference voltage source and temperature detection circuit, and uses an external clock when working. XPT2046 can be powered by a single power supply with a power supply voltage range of 2.7V to 5.5V. The reference voltage value directly determines the input range of the ADC. The reference voltage can use the internal reference voltage or directly input a reference voltage in the range of 1V to VCC from the outside (the external reference voltage source must have a low output impedance). The X, Y, Z, VBAT, Temp and AUX analog signals enter the ADC after being selected by the on-chip control register. The ADC can be configured in single-ended or differential mode. When VBAT, Temp and AUX are selected, it can be configured in single-ended mode; when used as a touch screen, it can be configured in differential mode, which can effectively eliminate the measurement error caused by the parasitic resistance of the drive switch and external interference, and improve the conversion accuracy. The
following figure shows the typical working circuit of XPT2046:
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XPT2046 has four pins, which are used to connect to the FPC of the four-wire resistive screen, namely XP, XN, YP, and YN, which are connected to the positive and negative ends of the X electrode and the positive and negative ends of the Y electrode of the corresponding four-wire resistive screen. Each of these four pins can work in two states, namely power supply/GND output and ADC input. For example, when setting the ADC to work in differential mode, when measuring the coordinates in the X direction, XP outputs VCC and XN is connected to GND. At this time, YP and YN are connected to the ADC as the differential input pins of the ADC, and the X position of the current touch point is obtained by measuring the voltage difference between YP and YN. Similarly, when measuring the coordinates in the Y direction, YP outputs VCC and YN is connected to GND. At this time, XN and XP are connected to the ADC as the differential input pins of the ADC, and the Y position of the current touch point is obtained by measuring the voltage difference between YP and YN.
XPT2046 control and drive scheme
After understanding the interface circuit of XPT2046, we can control the chip through the main control MCU or FPGA to realize the reading of coordinates. In order to correctly read the X and Y coordinates, it is necessary to read and write data according to the control protocol specified by the chip. XPT2046 needs to complete two conversions to read the X and Y coordinates once. A single conversion can only get a single X or Y coordinate. Therefore, we must control it twice to get the result. As for whether the object of each conversion is the X or Y coordinate, it is determined by the control word sent by the controller. The ADC can be configured as single-ended or differential mode during conversion. The specific control word is driven by the main control MCU to drive the DIN signal transmission at the beginning of each transmission. The following figure shows the typical 24-clock cycle conversion control timing of XPT2046:
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The XPT2046 data interface is a serial interface, and its typical working timing is shown in the figure above. The signals shown in the figure come from a microcontroller or a data signal processor with a basic serial interface. The communication between the processor and the converter requires 8 clock cycles, and synchronous serial interfaces such as SPI, SSI and Microwire can be used. A complete conversion requires 24 serial synchronous clocks (DCLK) to complete. The
first 8 clocks are used to input the control byte through the DIN pin. When the converter obtains enough information about the next conversion, it then sets the input multiplexer and reference source input according to the information obtained, and enters the sampling mode. If necessary, the touch panel driver will be started. After 3 multiple clock cycles, the control byte is set and the converter enters the conversion state. At this time, the input sample-and-hold enters the holding state, and the touch panel driver stops working (single-ended working mode). The next 12 clock cycles will complete the real analog-to-digital conversion. If it is a metric ratio conversion method (SER/DFR——＝0), the driver will continue to work during the conversion process, and the 13th clock will output the last bit of the conversion result. The remaining 3 multi-clock cycles will be used to complete the last byte ignored by the converter (DOUT is set low).
The control word input by DIN is shown in the following table. It is used to start conversion, address, set ADC resolution, configure and power down the XPT2046.
Start bit: The first bit, that is, S bit. The first bit of the control word must be 1, that is, S = 1. All inputs will be ignored before the start bit is detected by the DIN pin of the XPT2046.
Address: The next 3 bits (A2, A1 and A0) select the current channel of the multiplexer (see Table 1 and Table 2), touch screen drive and reference source input.
MODE: Mode selection bit, used to set the resolution of the ADC. MODE = 0, the next conversion will be 12-bit mode; MODE = 1, the next conversion will be 8-bit mode.
SER/DFR: The SER/DFR bit controls the reference source mode, selecting single-ended mode (SER/DFR = 1) or differential mode (SER/DFR = 0). In X-coordinate, Y-coordinate and touch pressure measurement, differential operation mode is preferred for best performance. The reference voltage comes from the voltage of the switch driver. In single-ended mode, the reference voltage of the converter is fixed to the voltage of VREF relative to the GND pin (see Table 1 and Table 2 for more details).
PD0 and PD1: Table 5 shows the relationship between power-down and internal reference voltage configuration. The internal reference voltage of the ADC can be turned off or on independently, but additional time is required for the internal reference voltage to stabilize to the final stable value before conversion; if the internal reference source is in power-down state, ensure that there is enough wake-up time. The ADC requires immediate use without wake-up time. In addition, it should be noted that when BUSY is high, the internal reference source is prohibited from entering power-down mode. After the channel of XPT2046 is changed, if you want to turn off the reference source, you need to rewrite the command to XPT2046.
Table 1 Correspondence between address and channel in single-ended mode6
Table 2 Correspondence between addresses and channels in differential mode
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Table 3 Function of each bit in the control field
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Table 4 Detailed description of each bit function of the control field
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Table 5 PD bit function description
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The above explains the timing of a single conversion through the conversion timing of 24 clock cycles. In practical applications, in order to improve the conversion efficiency, XTP2046 provides 16-clock conversion mode and 15-clock conversion mode. The control bit of
the 16-clock cycle conversion
n+1 conversion can overlap with the nth conversion, so a conversion can be completed with 16 clock cycles, as shown in Figure 16. Figure 16 also shows that the serial communication between the processor and the converter can be carried out independently in both directions. At this time, each conversion must be completed within 1.6mS after the start (receiving start), otherwise the signal sampled by the input sampling and holding circuit will gradually be discharged and attenuated, affecting the conversion result. In addition, the existence of another serial communication during the conversion process will cause XPT2046 to work in full power consumption state.
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8-bit bus interface, no DCLK clock delay 16 clock cycle conversion timing
In this mode, the minimum value of DCLK clock high level and low level is required to be 200ns, that is, the clock cycle of DCLK is 2.5MHz.
15 clock cycle conversion
The figure below shows the fastest timing of XPT2046. This method does not support the serial interface of most microcontrollers and digital signal processors, because they generally do not provide 15-cycle serial transmission. However, this method is suitable for FPGA and ASIC. It should be noted that this effectively increases the maximum conversion rate of the converter.
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Fastest conversion rate, 15 clock cycle conversion
In order to improve data throughput without affecting output accuracy, XPT2046 can adopt 8-bit conversion mode. Switch to 8-bit conversion mode and complete a conversion 4 clocks in advance. Not only is each conversion shortened by 4 bits (data throughput increased by 25%), but also due to the reduction in accuracy, it can work at a faster conversion rate, the clock speed can be increased by 50%, and the increase in clock speed and the reduction in conversion cycle can increase the conversion rate by 2 times.
XPT2046 driver design
Through the above introduction, we understand the working principle of resistive touch screens and the characteristics and timing interface of the commonly used touch controller XPT2046. Next, we will use Verilog to design a logic drive circuit that can control XPT2046 to complete coordinate conversion and finally obtain the touch coordinate point based on the interface characteristics of XPT2046 and the working characteristics of FPGA.
The designed controller is expected to have the following characteristics:
1. 12-bit conversion accuracy
2. High conversion efficiency
3. Use pen interrupt
4. Use differential mode to measure coordinates
In addition, according to engineering practice application experience, there will be jitter during the touch screen pressing process. Therefore, we need to perform jitter filtering on the conversion results. The simplest filtering algorithm is to use it multiple times, remove the maximum and minimum values, and calculate the average value. That is, we need to sample multiple times in succession, and then process the sampled results, and then use them as the final XY coordinates for the next level.
The above requirements are mainly related to the control field.
Condition 1, to obtain 12-bit sampling accuracy, according to Table 4, the third bit MODE of the control field should be 0.
Condition 2, to achieve high conversion efficiency, since we use FPGA for control, we can use a dedicated 15-clock cycle conversion timing.
Condition 3, using pen mode, set PD to 00 during the conversion process.
Condition 4, set it to differential mode, and set SER/DFR bit to 0.
When actually converting, according to Table 2, when measuring the X coordinate, set A2-A0 to 101. When measuring the Y coordinate, set A2-A0 to 001.
In order to achieve multiple measurements and average values, you can choose to perform 18 X-coordinate and Y-coordinate conversions each time a pen interruption is detected, then find the maximum and minimum values and remove them, and then divide the remaining 16 results by 16 (shift right 4 bits) to obtain the filtered value of the coordinates of the current position.
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According to the timing interface provided by XPT2046, the most convenient way to implement this control interface is to use a linear sequencer. Because it is completely known what data needs to be sent or read at each rising or falling edge of DCLK, it conforms to the design characteristics of a linear sequencer.
Design and implementation: Detailed comments are made in this example code, and we will not explain it line by line in this example. Please point out the parts you don't understand when you are studying, so that we can provide targeted supplementary explanations.
XPT2046 driver code
module xpt2046(
Clk50m,
Rst_n,
EN,
X_Value,
Y_Value,
Get_Flag,
PenIrq_n,
DCLK,
DIN,
DOUT,
CS_N,
BUSY
);
input Clk50m;
input Rst_n;
input EN;
output reg [11:0]X_Value;
output reg [11:0]Y_Value;
output reg Get_Flag;
input PenIrq_n;
input BUSY;
output reg DCLK;
output reg DIN;
output reg CS_N;
input DOUT;
wire pen_flag;
wire pen_state;
reg [4:0]DIV_CNT;//Get a sampling clock that is twice the DCLK clock to generate DCLK
reg [5:0]CLK_GEN_CNT;//Generate DCLK clock counter
reg [5:0]CONV_CNT;//Record how many conversions have been completed
reg [19:0]PEN_CNT;
reg DCLK2X;
reg CONV_DONE;
reg [11:0]Dtmp;
reg EN_CONV;
reg [16:0]tmp_X_Value,tmp_Y_Value;
reg [11:0]X_MAX,X_MIN,Y_MAX,Y_MIN;
reg r_Get_Flag;
localparam S = 1'b1; //Start bit
localparam MODE = 1'b0; //Sampling accuracy
localparam SER_DFR = 1'b0; //Single-ended/differential sampling mode
localparam PD = 2'b00; //Power consumption control
parameter CONV_TIMES = 36; //Calculate the average value every few conversions
parameter FILTER_PARAM = 4; //Divide by 16 == right shift 4 bits
parameter CNT_TOP = 20'd499999; //Filter and delay the PEN pin signal
wire [2:0]ADDR; //Sampling channel control
assign ADDR = (CONV_CNT[0])?3'b101:3'b001; //CONV_CNT value is an even number, select the measurement of X channel
wire cnt_full;//PEN pin signal filter counter count full flag
//PEN pin delay filter counter
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
PEN_CNT <= 20'd0;
else if(!PenIrq_n)begin //The pen stroke is low levelif
(cnt_full) //Count full and return to
zeroPEN_CNT <= 20'd0;
else //Not full and accumulatePEN_CNT
<= PEN_CNT + 1'b1;
end else //The pen stroke is high level, counting is prohibitedPEN_CNT
<= 20'd0;
assign cnt_full = (PEN_CNT == CNT_TOP);
assign pen_state = cnt_full;//When the PenIrq_n pin is low level, a pen_state signal is generated every time the count is full, triggering 36 samplings
//2x DCLK sampling clock division counter
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
DIV_CNT <= 5'd0;
else if(EN_CONV)begin
if(DIV_CNT == 5'd24)
DIV_CNT <= 5'd0;
else
DIV_CNT <= DIV_CNT + 1'b1;
end
else
DIV_CNT <= 5'd0;
//Generate 2x DCLK enable clock
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
DCLK2X <= 1'b0;
else if(DIV_CNT == 5'd24)
DCLK2X <= 1'b1;
else
DCLK2X <= 1'b0;
//Technique the 2x DCLK sampling clock to generate the basic sequence of the sequence machine
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
CLK_GEN_CNT <= 6'b0;
else if(EN_CONV)begin
if(DCLK2X)begin
if(CLK_GEN_CNT == 6'd45)//After counting to 46, return to 16 and start counting again
CLK_GEN_CNT <= 6'd16;
else
CLK_GEN_CNT <= CLK_GEN_CNT + 1'b1;
end
end
else
CLK_GEN_CNT <= 6'b0;
//Control the sequence according to the CLK_GEN_CNT value, send the control word and read the sampling result
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)begin
DIN <= 1'b1;
Dtmp <= 12'd0;
DCLK <= 1'd0;
CONV_CNT <= 6'd0;
end
else if(EN_CONV)begin
if(DCLK2X)begin
case(CLK_GEN_CNT)
0:begin DIN <= S; DCLK <= 1'b0; end //Send the first conversion start bit
1:begin DCLK <= 1'b1; end
2:begin DIN <= ADDR[2]; DCLK <= 1'b0; end //Send A2
3:begin DCLK <= 1'b1; end
4:begin DIN <= ADDR[1]; DCLK <= 1'b0; end//Send A1
5:begin DCLK <= 1'b1; end
6:begin DIN <= ADDR[0]; DCLK <= 1'b0; end//Send A0
7:begin DCLK <= 1'b1; end
8:begin DIN <= MODE; DCLK <= 1'b0; end//Send sampling accuracy setting bit
9:begin DCLK <= 1'b1; end
10:begin DIN <= SER_DFR; DCLK <= 1'b0; end//Send ADC input mode bit
11:begin DCLK <= 1'b1; end
12:begin DIN <= PD[1]; DCLK <= 1'b0; end//Send power consumption control bit PD1
13:begin DCLK <= 1'b1; end
14:begin DIN <= PD[0]; DCLK <= 1'b0; end //Send power consumption control bit PD0
15:begin DCLK <= 1'b1; end
16:begin DIN <= 0; DCLK <= 1'b0; end //Wait for the sample and hold circuit to work
17:begin DCLK <= 1'b1; end
18:begin DIN <= 0; DCLK <= 1'b0; end
19:begin Dtmp[11] <= DOUT; DCLK <= 1'b1; end //Read the 11th bit conversion result
20:begin DIN <= 0; DCLK <= 1'b0; end
21:begin Dtmp[10] <= DOUT; DCLK <= 1'b1; end //Read the 10th bit conversion result
22:begin DIN <= 0; DCLK <= 1'b0; end
23:begin Dtmp[9] <= DOUT; DCLK <= 1'b1; end//Read the 9th bit of conversion result
24:begin DIN <= 0; DCLK <= 1'b0; end
25:begin Dtmp[8] <= DOUT;DCLK <= 1'b1; end//Read the 8th bit of conversion result
26:begin DIN <= 0; DCLK <= 1'b0; end
27:begin Dtmp[7] <= DOUT; DCLK <= 1'b1; end//Read the 7th bit of conversion result
28:begin DIN <= 0; DCLK <= 1'b0; end
29:begin Dtmp[6] <= DOUT; DCLK <= 1'b1; end//Read the 6th bit of conversion result
30:begin DIN <= S; DCLK <= 1'b0; end //Send the control word starting bit
31 for the next conversion:begin Dtmp[5] <= DOUT; DCLK <= 1'b1; end //Read the 5th bit conversion result
32: begin DIN <= ADDR[2]; DCLK <= 1'b0; end //Send A2 for the next conversion
33: begin Dtmp[4] <= DOUT; DCLK <= 1'b1; end
34: begin DIN <= ADDR[1]; DCLK <= 1'b0; end //Send A1 for the next conversion
35:begin Dtmp[3] <= DOUT; DCLK <= 1'b1; end
36:begin DIN <= ADDR[0]; DCLK <= 1'b0; end//Send A0 for the next conversion
37:begin Dtmp[2] <= DOUT; DCLK <= 1'b1; end
38:begin DIN <= MODE; DCLK <= 1'b0; end//Send the sampling precision setting bit for the next conversion
39:begin Dtmp[1] <= DOUT; DCLK <= 1'b1; end
40:begin DIN <= SER_DFR; DCLK <= 1'b0; end//Send the ADC input mode bit for the next sampling
41:begin Dtmp[0] <= DOUT; DCLK <= 1'b1; CONV_CNT <= CONV_CNT + 1'b1; end
42:begin DIN <= PD[1]; DCLK <= 1'b0; end//Send power control bit PD1
43:begin DCLK <= 1'b1; end
44:begin DIN <= PD[0]; DCLK <= 1'b0; end//Send power control bit PD0
45:begin DCLK <= 1'b1; CONV_DONE <= 1'b1; end
endcase
end else
CONV_DONE <= 1'b0;
end else if(!EN_CONV)begin
CONV_CNT <= 0;
CONV_DONE <= 1'b0;
end
//Accumulate the sampling results of the X channel for 18 times out of 36 samples
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
tmp_X_Value <= 17'd0;
else if(EN_CONV == 1'b0)
tmp_X_Value <= 17'd0;
else if(CONV_DONE && CONV_CNT[0])//Conversion completed, conversion count is an odd number, add the conversion result to the X temporary register
tmp_X_Value <= tmp_X_Value + Dtmp;
//Record the maximum value of 18 X channel samples
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
X_MAX <= 12'd0;
else if(EN_CONV == 1'b0)
X_MAX <= 12'd0;
else if(CONV_DONE && CONV_CNT[0])begin//Conversion completed, conversion count is an odd number, determine whether the current value is greater than the stored maximum value
if(Dtmp > X_MAX)
X_MAX <= Dtmp;
else
X_MAX <= X_MAX;
end
//Record the minimum value of 18 X channel samples
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
X_MIN <= 12'd0;
else if(EN_CONV == 1'b0)
X_MIN <= 12'd4095;
else if(CONV_DONE && CONV_CNT[0]) CONV_CNT[0])begin //Conversion completed, conversion count is odd, determine whether the current value is less than the stored minimum valueif
(Dtmp < X_MIN)
X_MIN <= Dtmp;
else
X_MIN <= X_MIN;
end
//Accumulate the sampling results of the Y channel for 18 times out of 36 samplesalways
@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
tmp_Y_Value <= 17'd0;
else if(EN_CONV == 1'b0)
tmp_Y_Value <= 17'd0;
else if(CONV_DONE && (!CONV_CNT[0])) //Conversion completed, conversion count is even, accumulate the conversion result to the Y temporary registertmp_Y_Value
<= tmp_Y_Value + Dtmp;
//Record the maximum value of 18 Y channel samplesalways
@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
Y_MAX <= 12'd0;
else if(EN_CONV == 1'b0)
Y_MAX <= 12'd0;
else if(CONV_DONE && (~CONV_CNT[0]))begin //Conversion completed, conversion count is odd, determine whether the current value is greater than the stored maximum value
if(Dtmp > Y_MAX)
Y_MAX <= Dtmp;
else
Y_MAX <= Y_MAX;
end
//Record the minimum value of 18 Y channel samples
always@(posedge Clk50m or negedge Rst_n) if(!Rst_n) Y_MIN <= 12'd0; else if
(EN_CONV == 1'b0) Y_MIN <= 12'd4095; else if(CONV_DONE && (~CONV_CNT[0])) begin //Conversion completed, conversion count is odd, determine whether the current value is greater than the stored maximum
value if(Dtmp > Y_MAX)
Y_MAX <= Dtmp; else
Y_MAX <= Y_MAX;
end //Record the minimum value of 18 Y channel samples always@(posedge Clk50m or negedge Rst_n) (~CONV_CNT[0]))begin//Conversion completed, conversion count is an odd number, determine whether the current value is less than the stored minimum valueif
(Dtmp < Y_MIN)
Y_MIN <= Dtmp;
else
Y_MIN <= Y_MIN;
end
//Enable a 36-time conversionalways
@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
EN_CONV <= 1'b0;
else if(EN)begin
if(pen_state)
EN_CONV <= 1'b1;
else if((CONV_CNT == CONV_TIMES) && CLK_GEN_CNT == 29)//Conversion completed, align 15-cycle timing
EN_CONV <= 1'b0;
else
EN_CONV <= EN_CONV;
end
else
EN_CONV <= 1'b0;
//
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
r_Get_Flag <= 1'b0;
else if((CONV_CNT == CONV_TIMES) && CONV_DONE)
r_Get_Flag <= 1'b1;
else
r_Get_Flag <= 1'b0;
always@(posedge Clk50m)
Get_Flag <= r_Get_Flag;
always@(posedge Clk50m)
CS_N <= ~EN_CONV;
reg [11:0]r_X_Value,r_Y_Value;
//Calculate the current X mean value, X mean value = (18 accumulated values - maximum value - minimum value) / 16
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
r_X_Value <= 12'd0;
else if(r_Get_Flag)
r_X_Value <= (tmp_X_Value - X_MAX - X_MIN) >> FILTER_PARAM;
else
r_X_Value <= r_X_Value;
//Calculate the current Y average, Y average = (18 times accumulated value - maximum value - minimum value) / 16
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
r_Y_Value <= 12'd0;
else if(r_Get_Flag)
r_Y_Value <= (tmp_Y_Value - Y_MAX - Y_MIN) >> FILTER_PARAM;
else
r_Y_Value <= r_Y_Value;
//Store the last X result as output, in order to filter out the last conversion result, because the last conversion result has a press-release moment, the result is not stable
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
X_Value <= 12'd0;
else if(r_Get_Flag)
X_Value <= r_X_Value;
//Store the last Y result as output, in order to filter out the last conversion result, because the last conversion result has a press-release moment, the result is not stable
always@(posedge Clk50m or negedge Rst_n)
if(!Rst_n)
Y_Value <= 12'd0;
else if(r_Get_Flag)
Y_Value <= r_Y_Value;
endmodule
XPT2046 Design Verification
`timescale 1ns/1ns
module xpt2046_tb;
reg Clk50m;
reg Rst_n;
reg EN;
wire [11:0]X_Value;
wire [11:0]Y_Value;
wire Get_Flag;
reg PenIrq_n;
reg BUSY;
wire DCLK;
wire DIN;
wire CS_N;
reg DOUT;
initial Clk50m = 1;
always #10 Clk50m = ~Clk50m;
initial begin
Rst_n = 0;
PenIrq_n = 1;
EN = 0;
#201;
Rst_n = 1;
EN = 1;
#300;
PenIrq_n = 0;
#5000000;
PenIrq_n = 1;
#5000000;
$stop;
end
// initial begin
// DOUT = 1'b0;
// forever begin
// DOUT = ~DOUT;
// #30154;
// end
// end
initial DOUT = 1;
xpt2046 xpt2046(
.Clk50m(Clk50m),
.Rst_n(Rst_n),
.EN(EN),
.X_Value(X_Value),
.Y_Value(Y_Value),
.Get_Flag(Get_Flag),
.PenIrq_n(PenIrq_n),
.DCLK(DCLK),
.DIN(DIN),
.DOUT(DOUT),
.CS_N(CS_N),
.BUSY(BUSY)
);
endmodule
The following is a simple XPT2046 test script. This test script does not generate complex stimuli, but only generates clock and stroke interrupts to observe whether the corresponding control signals work normally during the entire conversion process.
XPT2046 verified on the development board
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