TMS320F28335 Interrupt Management Module PIE

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TMS320F28335 Interrupt Management Module PIE [Copy link]

The PIE module has so many peripherals to manage, so there must be corresponding response sequences and registers that need to be configured.
In the PIE module, each group of interrupts has a corresponding interrupt flag bit (PIEIFRx) and enable bit (PIE-IERx.y). In addition, each group of PIE interrupts (INT1~INT12) has a response flag bit (PIEACK). Figure 6.5 shows the operation flow of the PIE hardware when PIEIFR and PIEIER are set differently.

Once an interrupt is generated by the PIE controller, the corresponding interrupt flag bit (PIEIFRx.y) will be set to 1. If the corresponding PIE interrupt enable bit is also set to 1, PIE will check the corresponding PIEACKx to determine whether the CPU is ready to respond to the interrupt. If the corresponding PIEACKx bit is cleared, PIE will request an interrupt from the CPU; if PIEACKx is set to 1, PIE will wait until the corresponding PIEACKx is cleared before requesting an interrupt from the CPU. PIE controls only one interrupt in each group by controlling the PIEACKx bit. Once responded, PIEACKX needs to be cleared accordingly so that it can respond to the subsequent interrupts in the group.

For example, if you want the CPU to respond to the INT1.1 interrupt,
you need

PIEIFR1.1 Flag bit 1
PIEIER1.1 Enable bit 1
PIEACK1 Response flag bit cleared
IFR Global flag bit 1 (only for INT1-INT12)
IER Global interrupt enable bit 1 (only for INT1-INT12)