Share: TMS320F28335 project development record 9_28335 interrupt system
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1. Interrupt system
Here we must be very clear about the DSP's interrupt system.
C28XX has 16 interrupt sources, including 2 non-maskable interrupts RESET and NMI, timer 1 and timer 2 use interrupts 13 and 14 respectively. In this way, there are 12 interrupts directly connected to the peripheral interrupt expansion module PIE.
说的简单一点就是PIE通过12根线与28335核的12个中断线相连。而PIE的另外一側有12*8根线分别连接到外设，如AD、SPI、EXINT等等。
PIE manages 12*8=96 external interrupts in total. These 12 groups of major interrupts are controlled by the interrupt register IER of the 28335 core, that is, IER determines which group of major interrupts each interrupt belongs to (e.g. IER |= M_INT12; means we want to use the interrupt of the 12th group, but the CPU does not know which interrupt in the 12th group it is and needs to be determined by PIEIER).
Next, the lower 8 bits of the PIEIER register in the PIE module determine which interrupt this interrupt is in this group. These configurations must be told to the CPU (it is not difficult to imagine that PIEIER has a total of 12 interrupts, namely from PIEIER1 to PIEIER12).
In addition, the PIE module also has an interrupt flag register PIEIFR, and its lower 8 bits are the 8 flag bits from the external interrupt, and the CPU's IFR register is the flag register of the interrupt group. Therefore, all interrupt registers of the CPU control 12 groups of interrupts, and all interrupt registers of the PIE control 8 interrupts in each group.
In addition, which external interrupt do we use? There is also a corresponding external interrupt register. It should be noted that the external interrupt flag must be cleared by software. The interrupt flag registers of PIE and CPU are cleared by hardware.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.XINT2 = &ISRExint; //Tell the interrupt entry address
EDIS; // This is needed to disable write to EALLOW protected registers
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block使能PIE
PieCtrlRegs.PIEIER1.bit.INTx5 = 1; // Enable interrupt 5 in the first group
IER |= M_INT1; // Enable CPU first group interrupt
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
That is to say, each interrupt in the 12 groups must complete the same configuration as above, and the rest is to configure its own interrupt. As we mentioned EXINT, that is, when there is a low level outside, we enter the interrupt. Complete our program. Here we need to introduce that the GPIO port of DSP can be configured as an external interrupt port, and its configuration method is as follows:
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 0; //Select them as GPIO ports
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 0;
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 0;
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 0;
GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0; //Select them as input ports
GpioCtrlRegs.GPBDIR.bit.GPIO55 = 0;
GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0;
GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0;
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 0; //GPIO clock is the same as system clock and supports GPIO
GpioCtrlRegs.GPBQSEL2.bit.GPIO55= 0;
GpioCtrlRegs.GPBQSEL2.bit.GPIO56= 0;
GpioCtrlRegs.GPBQSEL2.bit.GPIO57= 0;
GpioIntRegs.GPIOXINT3SEL.bit.GPIOSEL = 54; //Interrupt 3 selects GPIO
GpioIntRegs.GPIOXINT4SEL.bit.GPIOSEL = 55;
GpioIntRegs.GPIOXINT5SEL.bit.GPIOSEL = 56;
GpioIntRegs.GPIOXINT6SEL.bit.GPIOSEL = 57;
XIntruptRegs.XINT3CR.bit.POLARITY = 0; //Trigger mode is falling edge trigger
XIntruptRegs.XINT4CR.bit.POLARITY= 0;
XIntruptRegs.XINT5CR.bit.POLARITY= 0;
XIntruptRegs.XINT6CR.bit.POLARITY= 0;
XIntruptRegs.XINT3CR.bit.ENABLE = 1; // Enable interrupt
XIntruptRegs.XINT4CR.bit.ENABLE = 1;
XIntruptRegs.XINT5CR.bit.ENABLE = 1;
XIntruptRegs.XINT6CR.bit.ENABLE = 1;
One thing to note is that external interrupts 1 and 2 can only be configured for GPIO0-GPIO31; external interrupts 3 and 4, 5, 6, and 7 can only be configured for GPIO32-GPIO63.
GPIO is divided into A (0-31), B (32-63), C (64-87); the C group cannot be configured as an external interrupt;
2. How to enable an interrupt?
3.How many levels of interrupt flags are there? What are their functions?
The interrupt flags mainly include three levels of CPU (with 16 flag bits), PIE (with 12 groups, each with 12 flag bits) and peripherals (some peripherals do not have them).
The flag latches the interrupt status after the interrupt occurs, which means that the interrupt occurs. After the CPU responds to the interrupt, it will automatically clear the CPU-level flag IFR bit and set the INTM bit at the same time to prevent other interrupts from occurring.
When the CPU takes the interrupt vector from PIE, PIE will automatically clear the PIE level flag bit PIEIFRx.y. Therefore, after entering the interrupt handler, all interrupt bits except the peripheral interrupt bits have been cleared.
The interrupt handler needs to clear PIEACKx and the peripheral interrupt flag (if any).
After the CPU responds to an interrupt, when entering the ISR, the global interrupt will be turned off by default. That is, when the interrupt service routine is running, no other interrupt will interrupt the CPU, including this interrupt event. In addition, if the interrupt flag of the peripheral is not cleared, the interrupt service function will not be looped into. This peripheral interrupt is blocked. Therefore, only the interrupt service routine that clears the peripheral can respond to the next peripheral interrupt. The same is true for PIEACK. If there is no PIEACK, all interrupts in this group are blocked.
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