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Chapter 5 GD32VF103C START PWM [Copy link]

 

First, let's take a look at the overview of RISC-V GD 's 103 timer.

This time we mainly refer to the official routine and use PWM mode

In PWM output mode ( PWM mode 0 is to configure CHxCOMCTL to 3'b110 , PWM mode 1 is to configure

CHxCOMCTL is 3'b111 ) , the channel is based on the values of the TIMERx_CAR register and the TIMERx_CHxCV register,

Output PWM waveform.

According to the counting mode, there are two types of PWM waves: EAPWM ( edge-aligned PWM) and CAPWM ( center-aligned PWM)

Refer to the PMW description of M3 , the two are similar

Here we choose PWM mode 0.

The following code starts to configure the PWM clock, GPIO , mode and parameters

Here the frequency division coefficient is 119, the period is 500 , and the main frequency is 108M. It is about 1.8khz if you want to manage it , and the duty cycle is 50%.

In fact, it is very similar to M3

Take a look

Basically the same, the main difference is in the channel parameter configuration, it seems that there are two more functions

timer_channel_output_pulse_value_config(TIMER0, TIMER_CH_0, 250);

timer_channel_output_mode_config(TIMER0, TIMER_CH_0, TIMER_OC_MODE_PWM0);

M3 is initialized by the structure

Let's look at the experimental phenomenon

This post is from Domestic Chip Exchange

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Thanks for sharing,,,,,, let me learn,,,,  Details Published on 2020-1-19 15:01
 
 

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Thanks for sharing,,,,,, let me learn,,,,
This post is from Domestic Chip Exchange
 
 
 

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