ARM programming mode and 7 modes

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ARM programming mode and 7 modes [Copy link]

ARM uses a 32-bit architecture

ARM Reading

--Byte: 8 bits

--Halfword: 16 bits (2 bytes) halfword

--Word: 32 bits (4 bytes)

Most ARM cores provide: core

--ARM instruction set (32 bit) (some take up memory and are fast)

--Thumb instruction set (16 bit) (saves memory but wastes time)

--Thumb2 instruction set (16 & 32bit) (ARM v7 (S5PV210) was launched around 2005)

Jazelle cores supports Java bytecode

/****************************************************** ***********************************************/

ARM has 7 basic working modes (6 privileged modes and one user mode)

----User (User mode): non-privileged mode, most tasks are performed in this mode

----FIQ (fast interrupt): This mode is entered when a high priority (fast) interrupt occurs -- |

----IRQ (normal interrupt): This mode is entered when a low priority (nomal) interrupt occurs |

----Supervisor (management mode): This mode will be entered when a reset or soft interrupt instruction is executed |-------Exception mode

----Abort (abnormal mode): This mode is entered when access is abnormal |

----Under (Undefined mode): This mode is entered when an undefined instruction is executed -- |

----System (system mode): a privileged mode that uses the same registers as User mode

Notice:

Except User mode which is Normal mode, the other six modes are Privilege mode.

Except for Sys mode, the other five modes in Privilege are abnormal modes.

The switching of various modes can be actively switched by the programmer through code (by writing the CPSR register); or the CPU can automatically switch in certain circumstances.

The permissions and accessible registers are different in each mode.

Why do we need so many modes?

CPU is hardware and OS is software. The design of software depends on the characteristics of hardware, and the design of hardware must take into account software needs to facilitate the implementation of software features.

The operating system has security level requirements, so the CPU is designed with multiple modes to facilitate the security level needs of various roles in the operating system.