Regarding the timing issues and acquisition issues of AD chip ADS1251

Mengmei

The timing of ADS1251 and the corresponding time of each part are shown in the figure below. Is there anything wrong with the reading code I wrote?

double GET_DOUT(void)
{
	unsigned int temp = 0x00000000;
	int i;
	
	SCLK(0);
	CLK(0);
	
	while(1)
	{
		CLK_Toggle();
		if(DOUT() == 1)
			break;
	}
	for(i=0;i<23;i++)	CLK_Toggle();
	CLK_Toggle();
	if(DOUT() != 0)
		return 1;
	for(i=0;i<5;i++)	CLK_Toggle();
	CLK_Toggle();
	if(DOUT() == 0)
		return 1;
	for(i=0;i<5;i++)	CLK_Toggle();
	
	CLK_Toggle();
	SCLK(1);
	if(DOUT())	temp |= 1;
	CLK_Toggle();
	SCLK(0);
	CLK_Toggle();
	CLK_Toggle();
	for(i=0;i<23;i++)
	{
		temp <<= 1;
		SCLK(1);
		if(DOUT())	temp |= 1;
		CLK_Toggle();
		CLK_Toggle();
		SCLK(0);
		CLK_Toggle();
		CLK_Toggle();
	}
	SCLK(1);
	CLK_Toggle();
	CLK_Toggle();
	SCLK(0);
	CLK_Toggle();
	CLK_Toggle();
	for(i=0;i<248;i++)	CLK_Toggle();
	
	Sample_Single = (double)temp;
	
	return 0;
}

DATASHEET said that the data reading frequency is f(CLK)/384, and the sampling frequency is f(CLK)/6. The reading frequency is much smaller than the sampling frequency, so there will be no delay in the read data caused by the register write explosion. ? However, there seems to be no obvious delay in the actual reading. Why is this?

littleshrimp

Your problem description is not very clear

Let me know my understanding. If the answer is not what you want, I will modify your question.

ADS1251 supports a maximum sampling rate of 20.833K, and the corresponding CLK clock is 8MHZ, which is the maximum value.

According to the FIGURE 12 timing, when you apply a clock to CLK, DOUT first outputs the DRDY signal, and the DRDY signal occupies 36 CLKs

When the 'high low high' signal of DRDY is output, you can read the conversion data. You need to read the data within the next 348 CLK cycles. This process is called DOUT. The total of DRDY+DOUT is 384 cycles. One conversion cycle, so 8MZH(CLK)/384=20.833KSPS maximum sampling rate comes from this.

Mengmei

littleshrimp published on 2019-11-17 18:33 The description of your question is not very clear. Please tell me my understanding. If the answer is not what you want, I will modify your question. ADS1251 supports a maximum of 20.833K...

What I mean is, during the time when the chip is reading (during DOUT after DRDY), is it still sampling? If so, will there be no delay in the data read next time (the next time DRDY data is generated? Was it sampled during the previous DOUT period)?

littleshrimp

Mengmei published on 2019-11-17 19:25 I mean, during the time of chip reading (during DOUT after DRDY) Is it still sampling? If so, then the next time it is read...

DRDY means that the data is ready. The current DOUT reads the last conversion result, and the current result It should be converting. After the conversion is completed, the DRDY signal will be output for the processor to read.

littleshrimp

Mengmei published on 2019-11-17 19:25 I mean, during the time of chip reading (during DOUT after DRDY) Is it still sampling? If so, then the next time it is read...

Data conversion depends on the CLK clock. As long as you ensure that CLK is continuous, there will be no delay.

Mengmei

littleshrimp published on 2019-11-17 22:22 Data conversion depends on the CLK clock. As long as you ensure that CLK is continuous, there will be no delay

Got it, thanks man

KKK.

Hello, I have been working on ads1254 related work recently. The timing of these two chips seems to be similar. Can you share your ads1251 driver code? Thank you! ! ! !