Class-D amplifier TAS5731M power-on timing analysis

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Class-D amplifier TAS5731M power-on timing analysis [Copy link]

 

In typical audio amplifier applications, audio DAC is usually used to output I2S signals to digital audio amplifiers for audio amplification. Audio DAC will determine whether it is in master or slave mode according to different peripheral configurations. Audio amplifiers usually act as slaves to receive I2S data from the master. CS5343 is an audio DAC that determines the master-slave mode by the level state of SDOUT in the I2S signal. When CS5343 and TAS5731M are used in combination, accurate power-on timing control of the two chips is crucial, otherwise there will be occasional no sound problems. The specific analysis is as follows.

TAS5731M Introduction:

TAS5731M is a 2*30W high-efficiency digital audio Class D amplifier with integrated DSP and 2.1 mode support. It can be used to drive stereo bridge speakers and accept a wide range of input data and transmission rates. TAS5731M can only work as a slave device and receive all external clock and data signals. Depending on the sampling rate, TAS5731M will directly perform PWM modulation at a switching rate of 384kHz to 352kHz when working.

TAS5731M power rail introduction:

TAS5731M has three power rails, PVDD, AVDD and DVDD. PVDD is used to power the half-bridge, and the power supply range supports 8V-24V. AVDD and DVDD are used to power the internal analog devices and digital circuits, respectively, and support 3.3V. In practical applications, the circuit can be simplified by using a 3.3V power supply for AVDD and DVDD.

TAS5731M power-on timing analysis:

Since the TAS5731M integrates DSP digital circuits and analog circuits such as half-bridge, the power-on timing is crucial to the normal operation of the device. The following Figure 1 shows the recommended power-on timing of the TAS5731M:

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Figure 1 TAS5731M recommended power-on sequence

To ensure the correct logic control inside the chip, it is necessary to ensure that AVDD/DVDD is powered on first and that each port is kept at a stable level. Before AVDD/DVDD reaches a stable level, the PDN and RESET pins must be kept at a low level to ensure that the chip is in a reset state. After AVDD/DVDD reaches a stable level, all logic level states have been determined, and then PDN, RESET and PVDD are pulled high and powered on to allow the chip to start working normally.

As can be seen from the annotations in Figure 1 above, the AVDD/DVDD value that can ensure the stability of the port level is about 3V. Combined with the TAS5731M datasheet, it is mentioned that when PVDD reaches 7.6V and AVDD/DVDD reaches 2.7V, all circuits can work normally. The reason is that there is a 1.8V LDO inside the TAS5731M, which is used to determine the level state of the port. The 1.8V LDO is powered by AVDD 3.3V. Due to the voltage drop of the LDO, when AVDD rises to 2.7V and above, the LDO starts to work and outputs a stable 1.8V voltage to determine the state of each logic level. The 1.8V LDO voltage can be measured through Pin18 VR-DIG.

Figure 2 below shows the waveforms of SDIN (yellow), AVDD (red), and SCLK (blue) of the TAS5731M at different test times under the same test conditions. The SDIN pin is pulled to AVDD through a pull-up resistor. It can be seen that before AVDD reaches 2.7V, the SDIN pin will have different high and low levels. In particular, when AVDD just reaches around 2.7V, the level of SDIN will suddenly switch, and then be raised to 3.3V by the pull-up resistor.

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Figure 2 TAS5731M SDIN/AVDD/SCLK waveform

Therefore, for the application scenario of audio DAC CS5343+TAS5731M, the audio DAC CS5343 will immediately detect the level of SDOUT after power-on, and the corresponding level of SDIN pin of TAS6731M will determine its working state. If the level is high, it is in master mode and outputs I2S signal; if the level is low, it is in slave mode and does not output I2S signal. If CS5343 detects the SDIN level before the AVDD level of TAS5731M reaches 2.7V, it will detect a low level, and CS5343 is considered to work in slave mode, resulting in no sound output.

There are two solutions for this situation:

1. Change the power-on sequence. Since the DAC needs to detect the SDIN level, it is possible to ensure that the TAS5731M power supply is stable before supplying power to the CS5343.

2. Audio DAC using hardware control mode, such as PCM1808+TAS5731M. PCM1808 can determine its master and slave modes through hardware pin level configuration.