Summary: About 2.4G NRF24L01 wireless module

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Summary: About 2.4G NRF24L01 wireless module [Copy link]

Through the study and practice of the 2.4G NRF24L01 wireless module and the reference to the Chinese and English manuals of NRF24L01, the following summary is made. If you want to have a deeper understanding of NRF24L01, please refer to the Chinese and English manuals.

1. Overview
NRF24L01 is a single-chip wireless transceiver chip that works in the 2.4G~2.5GHz universal ISM frequency band. The wireless transceiver includes: frequency generator, enhanced ShockBurst mode controller, power amplifier, crystal oscillator, modulator, and demodulator.

II. Basic functions
1) True GFSK monolithic transceiver chip
2) Enhanced ShockBurst function
3) Address and CRC check function
4) Wireless rate: 1 or 2Mbps
5) SPI interface rate: 0~8Mbps
6) 125 optional working channels
7) Low working voltage: 1.9~3.6V

3. Module Pin Description
The following takes the NRF24L01 module of Shenzhen Yunjia Technology Co., Ltd. as an example to explain the 2.4G NRF24L01 module pins. The module is shown in the figure below.

GND——GND
VCC——VCC
CE——digital input, RX or TX mode selection
CSN——digital input, SPI chip select signal
SCK——digital input, SPI clock
MOSI——digital input, slave SPI data input pin
MISO——digital output, slave SPI data output pin
IRQ——digital output, shieldable interrupt pin

4. SPI command macro definition of NRF24L01
#define NRF_READ_REG 0X00 //Read configuration register
#define NRF_WRITE_REG 0X20 //Write configuration register
#define RD_RX_PLOAD 0X61 //Read RX valid data: 1~32 bytes
#define WR_TX_PLOAD 0XA0 //Write TX valid data: 1~32 bytes
#define FLUSH_TX 0XE1 //Clear TX FIFO register, in transmit mode
#define FLUSH_RX 0XE2 //Clear RX FIFO register, in receive mode
#define REUSE_TX_PL 0XE3 //Reuse the previous packet of valid data
#define NOP 0xFF //No operation5

. NRF24L01 related register address macro definition
#define CONFIG 0X00 //Configuration register
#define EN_AA 0X01 //Enable automatic answer function
#define EN_RXADDR 0X02 //Receive address allowed
#define SETUP_AW 0X03 //Set address width
#define SETUP_RETR 0X04 //Establish automatic retransmission
#define RF_CH 0X05 //RF channel
#define RF_SETUP 0X06 //RF register
#define STATUS 0X07 //Status register
#define OBSERVE_TX 0X08 //Send detection register
#define CD 0X09 //Carrier detection
#define RX_ADDR_P0 0X0A //Data channel 0 receive address
#define RX_ADDR_P1 0X0B //Data channel 1 receive address
#define RX_ADDR_P2 0X0C //Data channel 2 receive address
#define RX_ADDR_P3 0X0D //Data channel 3 receive address
#define RX_ADDR_P4 0X0E //Data channel 4 receive address
#define RX_ADDR_P5 0X0F //Data channel 5 receiving address
#define TX_ADDR 0X10 //Transmit address
#define RX_PW_P0 0X11 //Receive data channel 0 valid data width
#define RX_PW_P1 0X12 //Receive data channel 1 valid data width
#define RX_PW_P2 0X13 //Receive data channel 2 valid data width
#define RX_PW_P3 0X14 //Receive data channel 3 valid data width
#define RX_PW_P4 0X15 //Receive data channel 4 valid data width
#define RX_PW_P5 0X16 //Receive data channel 5 valid data width
#define FIFO_STATUS 0X17 //FIFO status register

VI. NRF24L01 working mode
6.1. NRF24L01 mode configuration

6.2、Transmit mode function configuration
void NRF_TX_Mode(void)
{
NRF_CE_LOW();

NRF_WriteBuf(NRF_WRITE_REG+TX_ADDR,TX_ADDRESS,TX_ADR_WIDTH);
NRF_WriteBuf(NRF_WRITE_REG+RX_ADDR_P0,RX_ADDRESS,RX_ADR_WIDTH);
NRF_WriteReg(NRF_WRITE_REG+EN_AA,0x01); NRF_WriteReg(NRF_WRITE_REG+
EN_RXADDR,0x01);
NRF_WriteReg(NRF_WRITE_REG+SETUP_RETR,0x1a);
NRF_WriteReg (NRF_WRITE_REG+RF_CH,CHANNEL);
NRF_WriteReg(NRF_WRITE_REG+RF_SETUP,0x0f);
NRF_WriteReg(NRF_WRITE_REG+CONFIG,0x0e);

NRF_CE_HIGH();
delay_us(130);
}

6.3、Receive mode function configuration
void NRF_RX_Mode(void)
{
NRF_CE_LOW();

NRF_WriteBuf(NRF_WRITE_REG+RX_ADDR_P0,RX_ADDRESS,RX_ADR_WIDTH);
NRF_WriteReg(NRF_WRITE_REG+EN_AA,0X01);
NRF_WriteReg(NRF_WRITE_REG+EN_RXADDR,0X01); NRF_WriteReg(NRF_WRITE_REG
+RF_CH,CHANNEL); NRF_WriteReg(NRF_WRITE_REG
+RX_PW_P0,RX_PLOAD_WIDTH);
NRF_WriteReg(NRF_WRITE_REG +RF_SETUP,0x0f);
NRF_WriteReg(NRF_WRITE_REG+CONFIG,0x0f);

NRF_CE_HIGH();
}

6.4、Transmit and receive mode description
1) In transmit mode, CE must be pulled high for at least 10us.
2) NRF24L01 can receive data from 6 different channels in receive mode. Each data channel uses a different address but shares the same channel.
3) Data channel 0 is the only data channel that can be configured with a 40-bit self address. Data channels 1 to 5 are all 8-bit self addresses and 32-bit shared addresses.
4) All data channels can be set to enhanced ShockBurst mode.

7. Packet format of NRF24L01
7.1. Packet format in enhanced ShockBurst mode
Preamble | Address (3~5 bytes) | 9 bits (flag bit) | Data (1~32 bytes) | CRC check (0/1/2 bytes)

7.2. Data packet format compatible with NRF2401 etc. in ShockBurst mode
Preamble | Address (3~5 bytes) | Data (1~32 bytes) | CRC check (0/1/2 bytes)

7.3. Data Packet Description
Preamble: Added in transmit mode, removed in receive mode, used to detect 0 and 1.
Address: 1) Address content is the receiver address
2) Address width can be 3, 4 or 5 bytes
3) Address can be configured for receive channel and transmit channel separately
4) Automatically removed from received data packets Address
Flags: 1) PID, data packet identification. Two of them are used to increase by one every time a new data packet is received.
2) Seven bits are reserved for future compatibility with other products
3) Not effective when NRF24L01 communicates with NRF2401/NRF24E1
Data: 1~32 bytes
CRC: CRC check is optional

8. Summary
1. For NRF24L01, when using it, pay attention to the same channel for both the sender and the receiver (NRF24L01 has a total of 40 optional channels)
2. Pay attention to the configuration of the register
3. The address should be unified