STM32W108 wireless RF module general IO interface

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STM32W108 wireless RF module general IO interface [Copy link]

General IO Function Description GPIO Ports The
24 GPIO pins can be divided into three groups of ports: PA, PB, and PC. The GPIOs in each group of ports are numbered 0-7 according to their bits in the GPIO register.

Note: Since the functions of the GPIO port registers are the same, the symbol Px is used to represent PA, PB, and PC. For example, GPIO_PxIN represents the registers GPIO_PAIN, GPIO_PBIN, and GPIO_PCIN.

Each of the three GPIO ports has the following registers, whose lower 8 bits correspond to the 8 GPIO pins in the port:

● GPIO_PxIN (input data register) returns the level of the pin (except in analog mode).

● GPIO_PxOUT (output data register) controls the output level in normal output mode.

● GPIO_PxCLR (Clear Output Data Register) clears the bits in GPIO_PxOUT.

● GPIO_PxSET (Set Output Data Register) sets the bits in GPIO_PxOUT.

● GPIO_PxWAKE (wake-up monitor register) specifies the pins that can wake up the STM32W108.

In addition to these registers, each port has a pair of configuration registers, GPIO_PxCFGH and GPIO_PxCFGL. These registers specify the basic operating mode for the port pins. GPIO_PxCFGL configures pins Px[3:0], GPIO_PxCFGH configures pins Px[7:4], and the symbol GPIO_PxCFGH/L refers to this pair of configuration registers.

The five GPIO pins PA6, PA7, PB6, PB7 and PC0 can achieve a stronger output current than the general standard general purpose output.

Each pin
has a 4-bit configuration value in the GPIO_PxCFGH/L register. For different GPIO modes and their corresponding 4-bit configuration values, refer to Table 6.1.

If a GPIO has two peripherals that can be used as data sources in multiplexed output mode, then in addition to the GPIO_PxCFGH/L registers, other registers are required to jointly determine which peripheral controls the output.

Timer 2 and the serial port controller can share a multiplexed output pin with multiple GPIOs. Some bits in the TIM2_OR register of Timer 2 control the output of Timer 2 to different GPIO pins, and some bits in the TIM2_CCER register enable the output of Timer 2. When the output of Timer 2 is enabled, they will override the output of the serial port controller. According to some bits in the register TIM2_OR, Table 6.2 shows the GPIO output mapping for Timer 2.

When the output is configured for serial port control, the serial interface mode register (SCx_MODE) determines how the GPIO pins are used.

The multiplexed outputs of PA4 and PA5 can provide both trace data packets PTI_EN and PTI_DATA and synchronize CPU trace data TRACEDATA2 and TRACEDATA3.

If a GPIO is not associated with a peripheral in alternate output mode, its output will be set to 0.