Inter-core communication mechanism of multi-core processor

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Inter-core communication mechanism of multi-core processor [Copy link]

After the multi-core processor is triggered to communicate by an interrupt, the corresponding registers are configured to complete the communication. TMS320C6678 has 16 main inter-core communication registers, including 8 IPC interrupt generation registers (IPCGR0~IPCGR7) and 8 IPC interrupt confirmation registers (IPCAR0~IPCAR7). By setting the last bit IPCG of the IPC interrupt generation register IPCGRx (0≤x≤7) to 1, an interrupt to core_x can be generated; bits 1 to 3 are reserved bits, and bits 4 to 31 (SRCS0~SRCS27) provide up to 28 interrupt sources that can be identified. Bits 0 to 3 of the IPC interrupt confirmation register IPCARx (0≤x≤7) are reserved bits, and bits 4 to 31 (SRCC0~SRCC27) correspond to 28 different interrupt sources. When SRCSx is set to 1, the register sets the SRCCx bit of the corresponding interrupt confirmation register to 1. When the interrupt is confirmed, the register sets both the SRCCx and the corresponding SRCSx bits to 0.

When a processor core of TMS320C6678 is ready to communicate with other processor cores, according to the interrupt event mapping table of TMS320C6678, event 91 is triggered, a maskable inter-core interrupt is generated, and the interrupt service routine is called. The interrupt service routine IPC_ISR function is designed as follows:

void IPC_ISR()

{

KICK0 = KICK0_UNLOCK;

KICK1 = KICK1_UNLOCK;

*(volatileuint32_t *) IPCGR[2] = 0x20;

*(volatileuint32_t *) IPCGR [2] |= 1;

KICK0 = KICK0_UNLOCK;

KICK1 = KICK1_UNLOCK;

}

Taking the interrupt of sending 0x20 information to core_2 as an example, the corresponding 0x20 information is stored in the SRCS bit to identify the interrupt source. At the same time, the last bit IPCG of the interrupt generation register IPCGR2 in the current CPU core is set to 1 to trigger the IPC interrupt. When the target processor core is triggered by the interrupt, it will automatically jump to the corresponding entry point in the interrupt exception vector table, read the current core interrupt generation register IPCGRx (0≤x≤7), and obtain the inter-core information sent by the communication initiator from the SRCS bit of the register. Then store the information in the corresponding interrupt confirmation register IPCARx, clear the SRCC and the corresponding SRCS bits, and receive the next inter-core interrupt. KICK0 and KICK1 are trap control registers used to avoid communication conflicts.