Original article by Mr. Gaosu | Jiang Jie
The current that doesn’t follow the usual path is a “thorn” in PCB design. Sometimes, even though the road to the sun is paved for it, it insists on taking the single-plank bridge, which makes people want to cry without tears.
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Just like a case Mr. Gaosu encountered before, the power output vias were arranged neatly and there were empty positions waiting, but the current chose to go far away instead of near, and picked a few vias that you didn’t expect to go all the way.
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The relative positions of the power supply module VRM and the power consumption end SINK are as follows.
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Among them, the VRM uses a DC-DC switching power supply, and the vias near the power output pins of the DC-DC peripheral inductor L5 are evenly distributed, and the spacing between the inner circle vias and the pins is d1=d2=d3 (partial enlarged picture is as follows).
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It seems that there is nothing wrong. As expected, the current will be evenly distributed at least on the inner circle vias closest to the L5 power output pin. However, when thinking about the relative position of the SINK end and the VRM end, some friends began to wonder, because current likes to take shortcuts (paths with lower resistance), so will the vias on the lower left, which are closer to the SINK end, have more current? Mr. Gaosuo thought so at first, but the simulation results were surprising: the via current distribution diagram shows that in the opposite direction of the current flow (white box area), there are several vias with larger currents. What's going on? !
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It is Mr. Gaosuo's style to get to the bottom of things. Through careful analysis of the via current, it is found that the via current is not only related to the spacing of the power output pins, but also seems to have some mysterious connection with the direction of the gaps in the via array.
Make bold assumptions, verify carefully, take difficulties lightly, and do it right away. First simplify the model, delete other devices and traces on the board, keep the connection between the inner power and ground planes, and at the same time, replace the VRM with a capacitor with power output at one end and ground at the other end, and adjust the relative position of the VRM and SINK. The simplified model is as follows.
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The distribution of the via current at the VRM end of the simplified model has begun to emerge, and it seems that some trends can be seen.
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To further illustrate the problem, we continue to adjust the notch direction of the via array and compare the current carrying capacity of the vias.
It seems that it is not comprehensive enough to only look at the situation when the array gap is symmetrical, so let's take a look at the current carrying when it is asymmetrical.
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I believe you have already seen the pattern: when the power output via and the pin spacing are the same, the via closest to the array gap carries the largest current. Why does this phenomenon occur?
Let's take a look at the current density diagram. Taking the power output pin on the left as an example, at the beginning, the current is evenly distributed around the pin. For the three directions where the vias are distributed, the current will quickly find the nearest via and flow to the inner power plane. And part of the current that escapes from the via array gap probably encounters this: when you start, you take a quick look and see that the road is flat and there is copper in front of you. There are no vias blocking the way. It's great. As you run, you find that there is no way. Someone shouts: "This road is blocked, turn!" So, most of the current that escaped suddenly changes direction and goes into the via closest to the gap.
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This content is originally created by yvonneGan
, a user of EEWORLD forum. If you want to reprint or use it for commercial purposes
, you must obtain the author's consent and indicate the source
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