Complete chip design process and tools

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Complete chip design process and tools [Copy link]

The IC design process can be divided into two parts: front-end design (also called logic design) and back-end design (also called physical design). There is no unified and strict boundary between these two parts. Any design related to the process can be called back-end design.

The main process of front-end design:

1. Specification formulation

Chip specifications, like a list of features, are design requirements that customers put forward to chip design companies (called Fabless design companies), including specific functions and performance requirements that the chip needs to achieve.

2. Detailed design

Based on the specifications proposed by customers, Fabless comes up with design solutions and specific implementation architectures, and divides module functions.

3. HDL Coding

Use hardware description language ( VHDL , Verilog HDL , companies in the industry generally use the latter) to describe and implement module functions in code, that is, describe the actual hardware circuit functions through HDL language to form RTL (register transfer level) code.

4. Simulation Verification

Simulation verification is to check the correctness of the coding design, and the verification standard is the specification formulated in the first step. See if the design accurately meets all the requirements in the specification. The specification is the golden standard for whether the design is correct or not. Any violation or non-conformity with the specification requires re-design and re-coding. Design and simulation verification are iterative processes until the verification results show full compliance with the specification standards. Simulation verification tools such as Mentor 's Modelsim , Synopsys ' VCS , and Cadence 's NC-Verilog can all perform design verification on RTL- level code. For this part, I generally use the first one - Modelsim . This part is called pre-simulation, and the simulation performed again after the synthesis of the logic part can be called post-simulation.

5. Logic Synthesis - Design Compiler

After the simulation verification is passed, logic synthesis is performed. The result of logic synthesis is to translate the HDL code of the design implementation into a gate-level netlist . Synthesis requires setting constraints, which is the standard that you hope the synthesized circuit will achieve in terms of target parameters such as area and timing. Logic synthesis needs to be based on a specific synthesis library. In different libraries, the area and timing parameters of the basic standard cell of the gate circuit are different. Therefore, if different synthesis libraries are selected, the synthesized circuits will have differences in timing and area. Generally speaking, after the synthesis is completed, simulation verification needs to be performed again (this is also called post-simulation, and the previous one is called pre-simulation). The logic synthesis tool is Synopsys 's Design Compiler , and the simulation tool can be any of the three simulation tools mentioned above.

6 、 STA

Static Timing Analysis ( STA ), static timing analysis, also belongs to the category of verification. It mainly verifies the circuit in terms of timing, checking whether the circuit has violations of setup time and hold time . This is the basic knowledge of digital circuits. When a register has these two timing violations, it is impossible to correctly sample and output data, so the digital chip function based on registers will definitely have problems. STA tools include Synopsys ' Prime Time .

7. Formal Verification

This is also the scope of verification, which verifies the synthesized netlist from a functional perspective ( STA is timing). The commonly used method is the equivalence check method, which uses the HDL design after functional verification as a reference to compare the synthesized netlist functions to see if they are functionally equivalent. This is done to ensure that the circuit function described by the original HDL is not changed during the logic synthesis process. Formal verification tools include Synopsys ' Formality . The front-end design process is temporarily written here. In terms of design level, the result of the front-end design is the gate-level netlist circuit of the chip.

Backend design flow Backend design flow:

1、DFT

Design For Test , design for testability. Chips often have built-in test circuits. The purpose of DFT is to consider future tests during design. A common method of DFT is to insert scan chains into the design and turn non-scan units (such as registers) into scan units. Regarding DFT , some books have detailed introductions, and it is easier to understand by comparing pictures. DFT tool Synopsys 's DFT Compiler

2. Floor Plan

Layout planning is to place the macro unit modules of the chip and determine the placement of various functional circuits in general, such as IP modules, RAM , I/O pins, etc. Layout planning can directly affect the final area of the chip. The tool is Synopsys 's Astro

3、CTS

Clock Tree Synthesis , clock tree synthesis, simply put, is the routing of the clock. Due to the global command role of the clock signal in the digital chip, its distribution should be symmetrically connected to each register unit, so that when the clock reaches each register from the same clock source, the clock delay difference is minimized. This is why the clock signal needs to be routed separately. CTS tool, Synopsys 's Physical Compiler

4. Place & Route

The wiring here is the ordinary signal wiring, including the routing between various standard units (basic logic gate circuits). For example, the 0.13um process or 90nm process we usually hear about is actually the minimum width that the metal wiring can achieve here, which is the channel length of the MOS tube from a microscopic perspective .

5. Parasitic parameter extraction

Due to the resistance of the wire itself, the mutual inductance between adjacent wires , and the coupling capacitance inside the chip, signal noise, crosstalk, and reflection will occur. These effects will cause signal integrity problems, resulting in signal voltage fluctuations and changes, and if serious, will cause signal distortion errors. It is very important to extract parasitic parameters for re-analysis and verification to analyze signal integrity issues. The tool Synopsys ' Star-RCXT

6. Layout physical verification

The physical layout after wiring is verified in terms of function and timing. There are many verification items, such as LVS ( Layout Vs Schematic ) verification. Simply put, it is the comparison and verification of the layout and the gate-level circuit diagram after logic synthesis; DRC ( Design Rule Checking ): Design rule checking, checking whether the connection spacing and connection width meet the process requirements, ERC ( Electrical Rule Checking ): Electrical rule checking, checking electrical rule violations such as short circuits and open circuits; etc. The tool is Synopsys ' Hercules. The actual back-end process also includes circuit power consumption analysis and DFM (Design for Manufacturability) problems that arise with the continuous advancement of manufacturing processes, which will not be discussed here. The completion of physical layout verification means that the entire chip design stage is completed, and the next step is chip manufacturing. The physical layout is handed over to the chip foundry (called Foundry ) in the GDSII file format to make actual circuits on the wafer silicon wafer, and then package and test it to get the chip we actually see.

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The reason is this, the process is very critical and complicated.