How to avoid electrical stress in chip design, do you know?

Do you know how to avoid electrical stress in chip design? When chip designers lead a sensitive pin of an op amp out of the chip, they usually think about whether the user will handle this pin carefully? Or will they just carelessly connect this pin directly to the alternating current? Connected? We all want to design good products that can handle the extremes of use our users put into them. So, how to prevent product failure caused by over-electrical stress in design?

OPA320 is one of the most typical operational amplifiers. Its maximum rated parameter table is shown in Figure 1. It describes the maximum allowable supply voltage of the chip, the maximum allowable input voltage and current of the pin. According to the additional note in the parameter sheet, if the pin input current is limited, then there is no need to limit the input voltage. Internal clamping diodes allow ±10mA input current. However, when the input voltage is much higher than the normal value, limiting the input current requires a larger input impedance, which increases noise, reduces bandwidth, and may also produce other errors.

The clamping diodes begin conducting when the input voltage exceeds the supply rail by approximately 0.6V. Generally, many devices can withstand larger currents, but when the voltage increases sharply, the probability of device failure increases.

By adding external diodes, the ability of the device to withstand large currents can be greatly improved, and the protection level of the device can also be improved. Common signal diodes on the market, such as the ubiquitous 1N4148, have very low conduction voltage drops (lab tests show that they are at least 100mV lower than the op amp's internal diodes). After being connected in parallel with the internal diode of the op amp, most of the current will flow to the external diode when encountering input overcurrent.

Schottky diodes have lower turn-on voltage, which improves protection performance. But the disadvantage is also obvious, its leakage current is too large. At room temperature, its reverse leakage current is usually microamps or greater, and increases as the temperature increases.

In addition, you also need a powerful enough power supply. Clamping diodes, whether internal or external to the op amp, require a relatively stable power supply to release energy. If the fault pulse is large enough to sink too much current into the power rail, raising (or pulling down the negative supply) supply voltage, the pulse will subject the supply terminals to excessive voltage stress, as shown in Figure 2. A typical linear power supply cannot sink current, so don't expect to be very stable using it as a power supply. Large bypass capacitors can be used to absorb large fault pulse currents. For continuous fault currents, Zener diodes can be added to the input pins and power supplies. The reverse breakdown voltage of the Zener diode should be just above the maximum supply voltage of the system, so that the Zener diode will be turned on only during a fault. For positive and negative power supply systems, the same protection circuits need to be designed on both power rails.

Despite these measures, the pin input voltage may still exceed the value in the maximum rating table, but the key problem is: the value in the maximum rating table is usually too conservative; chip damage is almost impossible at this voltage or current. . Generally speaking, if these parameters are significantly exceeded, device damage is unlikely (but not guaranteed). It is easy to clamp to a few volts higher than the value in the maximum ratings table while getting a lower failure rate. In many cases, the design goal is to reduce failure rates at a tradeoff between cost and performance.

There is no one solution that can deal with all situations, and no one protection circuit can meet all needs at the same time. Protection circuit schemes vary widely in different applications. Different op amps have different sensitivities, and the required protection levels also vary greatly. This may require some creativity on your part, and it's best to be your own expert. Although doing some testing in extreme environments will result in the loss of some op amps, this is necessary. The above is how to avoid electrical stress in chip design. I hope it can help you.