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How to add own image processing operations to the zynq video pipeline? [Copy link]

As the title says, I have now established a video channel on ZYNQ: The general situation of the channel is as follows:

/************config hls ip********/
voidConfigureHlsIP(XImgprocess_top *ImgProcess)
{
        ImgProcess->Control_bus_BaseAddress = XPAR_IMGPROCESS_TOP_0_S_AXI_CONTROL_BUS_BASEADDR;
        ImgProcess->IsReady = XIL_COMPONENT_IS_READY;
        XImgprocess_top_EnableAutoRestart(ImgProcess);
        XImgprocess_top_SetRows(ImgProcess, 480);
        XImgprocess_top_SetCols(ImgProcess,640);
        XImgprocess_top_InterruptDisable(ImgProcess, 0xFFFFFFFF);
        XImgprocess_top_InterruptGlobalDisable(ImgProcess);
        XImgprocess_top_Start(ImgProcess);
}
int main()
{
    init_platform();
        usleep(100000);
    print("Hello World\n\r");
    ConfigureHlsIP(&ImgProcess);
// MM2S
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x00, 0x008B);                // enable run, circular_park, GenlockEn, GenlockSrc
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x5C, 0x01000000);        // Start address of the 1st frame(3 frames in all)
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x60, 0x02000000);        // Start address of the 2nd frame(3 frames in all)
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x64, 0x03000000);        // Start address of the 3rd frame(3 frames in all)
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x58, 0x0780);                // Stride number
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x54, 0x0780);                // number of bytes per line(640 x 3)
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x50, 0x01E0);                // number of lines per frame(480)
//S2MM
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x30, 0x108B);                // enable run, circular_park
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xAC, 0x01000000);        // Start address of the 1st frame(3 frames in all)
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xB0, 0x02000000);        // Start address of the 2nd frame(3 frames in all)
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xB4, 0x03000000);        // Start address of the 3rd frame(3 frames in all)
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA8, 0x0780);                // Stride number
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA4, 0x0780);                // number of bytes per line(640 x 3)
        Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA0, 0x01E0);                // number of lines per frame(480)
return0;
}

But now there is a problem. This path is to collect camera data, then hls_IP processing, and then dma storage and image display. Now I want to add some simple operations on image data in SDK. How can I do it? This path is automatic, from image acquisition to image display. If I directly operate the image data in the memory address in SDK, data conflict will occur. What should I do? Please give me some ideas

This post is from FPGA/CPLD

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Eliminate zero response. . . . .   Details Published on 2019-9-12 15:16
 

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Eliminate zero response. . . . .

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