Tips for Setting the Baud Rate of the MSP430 Serial Port

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Tips for Setting the Baud Rate of the MSP430 Serial Port [Copy link]

Given a BRCLK clock source, the baud rate is used to determine the factor N that needs to be divided:
N = fBRCLK/Baudrate
The division factor N is usually a non-integer value, so at least one divider and a modulation stage are used to get as close to N as possible.
If N is equal to or greater than 16, UCOS16 can be set to select the oversampling baud Rate mode
Note: Round(): refers to rounding.
Low-Frequency Baud Rate Mode Setting
In low-frequency mode, the integer factor can be achieved by prescaling:
UCBRx = INT(N)
The fractional factor can be achieved by the modulator using the following nominal formula:
UCBRSx = round( ( N – INT(N) ) × 8 )
Increasing or decreasing the UCBRSx setting by one count may result in a lower maximum bit error rate for any given bit. If it is determined that this is the case, an accurate error calculation must be performed for each bit of the UCBRSx setting.

Example 1: 1048576Hz frequency driving asynchronous communication at 115200 baud rate
ACLK = REFO = ~32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz.
N = fBRCLK/Baudrate = 1048576/115200 = ~9.10
UCBRx = INT(N) = INT(9.10) = 9
UCBRSx = round( ( N – INT(N) )×8 )
= round( ( 9.10 – 9) × 8 )=round(0.8 )=1
UCA0CTL1 |= UCSSEL_2; // Select SMCLK as the clock
UCAxBR0 = 9;
UCAxBR1 = 0;
UCAxMCTL = 0x02; //7-4: UCBRFx, 3-1: UCBRSx, 0: UCOS16
UCBRSx is the 1st to 3rd bit of the UCAxMCTL register, so write 0x02 (00000010)

Example 2: Driving an asynchronous communication at 2400 baud at 32768 Hz ACLK = REFO = ~32768Hz, MCLK = SMCLK = DCO ~1.045MHz
N = fBRCLK/Baudrate = 32768/2400 = ~13.65
UCBRx = INT(N) = INT(13.65) = 13
UCBRSx = round( ( N – INT(N) )×8 )
= round( ( 13.65 – 13) × 8 )=round(5.2)=5
UCA0CTL1 |= UCSSEL_1; // Select ACLK as the clock
UCAxBR0 = 13; UCAxBR1 = 0 ;
UCAxMCTL = 0x0A; //7-4: UCBRFx, 3-1: UCBRSx, 0: UCOS16
UCBRSx is the 1st to 3rd bit of the UCAxMCTL register, so write 0x0A (00001010)

Oversampling Baud Rate Mode Setting
In oversampling mode, the divider is set as follows:
UCBRx = INT(N/16)
The first modulation stage is set as follows:
UCBRFx = round( ( (N/16) – INT(N/16) ) × 16 )
When more accuracy is required, UCBRSx can also be set to 0-7.
Example 1: Drive asynchronous communication at 9600 baud rate at 1048576Hz frequency
UCBRx = INT(N/16)=INT(fBRCLK/Baudrate/16)
UCBRx = INT(1048576Hz/(16*9600)) = INT(~6.8)
UCBRFx = round( ( (N/16) – INT(N/16) ) × 16 )
= round( ( 6.8 – 6 ) × 16 )=13
UCAxCTL1 |= UCSSEL_2; // Select SMCLK as clock
UCAxBR0 = 6; // 1MHz 9600
UCAxBR1 = 0; // 1MHz 9600
UCAxMCTL = 0xD1; //7-4:UCBRFx,3-1:UCBRSx,0:UCOS16
UCBRFx The register UCAxMCTL is bits 4-7, UCOS16 is bit 0, so write 0xD1 (11010001).
The specific register value is set in the MSP430F5438 User's Guide